Moves the LV_DRAW_DMA2D_HAL_INCLUDE to the soc instead of the development
kit since the hal include is the same across all boards using the soc.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The default SCK and COPI/MOSI pins on the Sparkfun Pro Micro RP2040
board correspond to `GPIO22` and `GPIO23` respectively[^1].
The existing pinctrl definitions in the `spi0_default` don't reflect
this (rather, they match the pinout of the Adafruit KB2040 MCU[^2]).
Update the board's respective pinctrl definitions to match the pinout.
[^1]: https://cdn.sparkfun.com/assets/e/2/7/6/b/ProMicroRP2040_Graphical_Datasheet.pdf
[^2]: https://learn.adafruit.com/assets/106984
Signed-off-by: Anant Thazhemadam <anant.thazhemadam@gmail.com>
Enable execution of i2c driver tests by adding i2c entry to
the list of supported peripherals.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Refactor the devicetree files for the Atmel SAM E70 and SAM V71 product
series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Introduce a base samx7x.dtsi for all members of the family, containing the
union of all supported peripherals. Specific product series can use
/delete-node/ in their DTSI (e.g. same70.dtsi) for removing peripherals not
present in that product series.
Replace pin-count-specific DTSI files (e.g. same70q19b.dtsi) with
pin-count-agnostic DTSI files (e.g. same70x19b.dtsi) as the pin-count is
not taken into account in these anyways, and adjust the relevant board
devicetrees accordingly.
As part of this refactoring, introduce support for the missing flash memory
density variants of the SAM E70 product series.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further changes to the SoC support
code (soc/atmel/sam/).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The heap and stack are now consistent with other ESP32-C3 boards in
tree. This is necessary for Bluetooth to not crash on boot.
Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
OCRAM region in Cortex-M4 memory map at 0x2020_0000 is simply an alias
to the M4 TCM at 0x1FFE_0000, which the zephyr,flash node was previously
set to. Using this base address for OCRAM allows the base address to
match the one used in the M7 memory map, which simplifies loading the M4
image from flash into RAM in the M7 init routine
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Since commit bda8ae8c3f ("drivers: clock_control: silabs: Add clock
control driver"), clock configuration is defined in Device Tree.
We can drop now unused configurations existing in board definitions.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add new test sample.sensor.thermometer_i3c, can't assign the same
platform with i2c, and i3c at the same time.
Support the shield on FRDM_MCXN236 board by I2C and I3C way.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
The two interrupt controller registers on 818x got spoonerized, oops.
Hilariously it actually worked (mostly) becuase the interrupt would
still be delivered, the controller isn't involved in the ACK/clear
process on thsi device, the and the set of pending interrupts was
masked against enabled ones. Found it by accident when I moved things
around and caught a "spurious" interrupt.
Also the 8195 DRAM region was all packed in a single block that doesn't
honor the two regions defined in the host devicetree. That's benign
from Zephyr (the memory in the hole actually is usable) but dangerous
for SOF as the second region is used by the host driver to allocate
DMA buffers and we can't touch it except as directed. Honor the
scheme used by the other devices.
Signed-off-by: Andy Ross <andyross@google.com>
Xtensa cache line sizes aren't an obtuse area of pedantry like they
are in x86. Different cores already in Zephyr are already using
variant cache line sizes (64 and 128 bytes are both common).
And I tripped over this by using the wrong value because the kconfig
was being inherited (incorrectly) from a default somewhere.
Xtensa exposes the correct value in core-isa.h (well, unless the
toolchain/hal gets messed up). Add a check to make sure that our
platform kconfig gets it right.
Note that qemu/dc233c was already getting this wrong, leaving the
value at the kconfig default of zero. That was benign (qemu doesn't
provide any cache emulation for incoherent DMA), but needs to be
fixed.
Signed-off-by: Andy Ross <andyross@google.com>
There are 4 Kconfig names about the "Draw Buffer". Rename 'VBD' to 'VDB'
in Kconfig option 'LV_Z_*VBD*_CUSTOM_SECTION' to make name consistent.
config LV_Z_VDB_ALIGN
int "Rending buffer alignment"
config LV_Z_VBD_CUSTOM_SECTION
bool "Link rendering buffers to custom section"
config LV_Z_DOUBLE_VDB
bool "Use two rendering buffers"
config LV_Z_VDB_SIZE
int "Rendering buffer size"
default 100 if LV_Z_FULL_REFRESH
And the draw buffer definition is now:
static uint8_t buf0[BUFFER_SIZE]
#ifdef CONFIG_LV_Z_VDB_CUSTOM_SECTION
Z_GENERIC_SECTION(.lvgl_buf)
#endif
__aligned(CONFIG_LV_Z_VDB_ALIGN);
Signed-off-by: Haiyue Wang <haiyuewa@163.com>
The stm32l562e_dk board uses a ft6x06 i2c controller for the touchscreen.
The zephyr driver ft5336 can control it.
Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
This introduces the pro micro nrf52840 board type,
commonly available as the cheapest nrf52840 development board,
and is based on the Nice!Nano
Signed-off-by: Camille BAUD <mail@massdriver.space>
This board contains both an NTC sensor dependings on a specific SPI ADC and
a TMP116 containing both a sensor and an EEPROM.
Align these driver initialization priorities with the devicetree
dependencies to avoid build failures with CONFIG_CHECK_INIT_PRIORITIES=y.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add the stm32f413h_disco target to the boards/st
Add the PLLi2S when needed by the USB or SDMMC or RNG.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
J-Link firmware images for silabs boards are not distributed by
SEGGER, fw update should be done with Simplicity Studio instead.
Signed-off-by: Daniel Fuchs <software@sagacioussuricata.com>
Based on board files for DK2601B. The EFR32xG24 Explorer Kit
(xG24-EK2703A) is similar to the DK2601B but does not have any
sensors onboard.
Signed-off-by: Daniel Fuchs <software@sagacioussuricata.com>
Add initial support for the RP2350's DMA peripheral, allow tests
under drivers/dma/loop_transfer to run on on the Raspberry Pi Pico 2,
and update the board's documentation.
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add initial support for the RP2350's PIO peripherals, extend the
existing example under samples/boards/raspberrypi/rpi_pico/uart_pio to
demonstrate this on the Raspberry Pi Pico 2, and update the board's
documentation.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
Add OpenOCD debugger support.
For now we will need Raspberry Pi'a forked version of OpenOCD from
https://github.com/raspberrypi/openocd .
The default adapter speed is set to match Raspberry Pi's documentation.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add UF2 Family ID for Raspberry Pi 2350 and build
UF2 image by default for Pico 2 board
Signed-off-by: Ryan Grachek <grachek@gmail.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
The Raspberry Pi Pico 2 is Raspberry Pi's first board fitted with their
RP2350A SoC.
This adds a minimal board definition, sufficient to build and run
`samples/hello_world` and `samples/basic/blinky` on the board. Images
can be run on the target using OpenOCD. Raspberry Pi's `picotool` can
create a UF2 binary, which ensures that errata RP2350-E10 is avoided
e.g.
```
> picotool uf2 convert build\rpi_pico2\hello_world\zephyr\zephyr.elf \
build\rpi_pico2\hello_world\zephyr\zephyr.uf2 \
--family rp2350-arm-s --abs-block`
```
Raspberry Pi Pico 2 is a low-cost, high-performance microcontroller
board with flexible digital interfaces. Key features include:
- RP2350A microcontroller chip designed by Raspberry Pi in the United
Kingdom
- Dual Cortex-M33 or Hazard3 processors at up to 150MHz
- 520KB of SRAM, and 4MB of on-board flash memory
- USB 1.1 with device and host support
- Low-power sleep and dormant modes
- Drag-and-drop programming using mass storage over USB
- 26x multi-function GPIO pins including 3 that can be used for ADC
- 2x SPI, 2x I2C, 2x UART, 3x 12-bit 500ksps Analogue to Digital
Converter (ADC), 24x controllable PWM channels
- 2x Timer with 4 alarms, 1x AON Timer
- Temperature sensor
- 3x Programmable IO (PIO) blocks, 12 state machines total for custom
peripheral support
- Flexible, user-programmable high-speed IO
- Can emulate interfaces such as SD Card and VGA
The Raspberry Pi Pico 2 comes as a castellated module which allows
soldering direct to carrier boards.
Only enable timer 0 for now. Timer 1 won't work correctly until the
rpi_pico HAL has picked up the fix for `hardware_alarm_irq_handler`. See
https://github.com/raspberrypi/pico-sdk/pull/1949 .
Added some documentation for the board itself (mostly aiming to refer to
canonical sources of information rather duplicate). Add entries in the
release notes where applicable.
boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp is a cropped and
compressed version of https://www.raspberrypi.com/documentation/microcontrollers/images/pico-2.png
which is released under the CC-BY-SA-4.0 license. See https://github.com/raspberrypi/documentation/blob/develop/LICENSE.md
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
