The sentry symbols that mark the ends of the newlib heap area were
being placed in cached memory, which violates the coherence rules.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Turns out that the user can configure the "zephyr.elf" name via
kconfig to be "something_else.elf" instead. And there's a test the
does this. Use the right variable; don't hardcode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was added early when we had (somewhat oddly) a log subsystem
backend but not a printk char_out hook. Now we have one backend that
works with both. No need, and this fixes build errors with a handful
of tests that specify LOG_MINIMAL (LOG_PRINTK requires the full log
subsystem and doesn't work with MINIMAL).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In commit efa05d1e42da ("soc/intel_adsp: Put initial stack into the
CPU0 interrupt stack") the "_end" symbol was accidentally removed from
the linker script. Newlib needs this to size its heap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Xtensa L1 cache layer has straightforward semantics accessible via
single-instructions that operate on cache lines via physical
addresses. These are very amenable to inlining.
Unfortunately the Xtensa HAL layer requires function calls to do this,
leading to significant code waste at the calling site, an extra frame
on the stack and needless runtime instructions for situations where
the call is over a constant region that could elide the loop. This is
made even worse because the HAL library is not built with
-ffunction-sections, so pulling in even one of these tiny cache
functions has the effect of importing a 1500-byte object file into the
link!
Add our own tiny cache layer to include/arch/xtensa/cache.h and use
that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of passing the crt1 _start function as the entry code for
auxiliary CPUs, use a tiny assembly stub instead which can avoid the
runtime testing needed to skip the work in _start. All the crt1 code
was doing was clearing BSS (which must not happen on a second CPU) and
setting the stack pointer (which is wrong on the second CPU).
This allows us to clean out the SMP code in crt1.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr's normal architecture is to do all initialization in the
interrupt stacks. The CAVS code was traditionally written to start
the stack at the end of HP-SRAM, where it has no protection against
overlap with other uses (e.g. MP startup used the same region for
stacks and saw cache collisions, and the SOF heap lives in this area
too). Put it where Zephyr expects and we'll have fewer surprises.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The kernel passes the CPU's interrupt stack expected that it will
start on that, so do it. Pass the initial stack pointer from the SOC
layer in the variable "z_mp_stack_top" and set it in the assembly
startup before calling z_mp_entry().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There's no need to muck with the cache directly as long as we're
careful about addressing the shared start record through an uncached
volatile pointer.
Correct a theoretical bug with the initial cache invalidate on the
second CPU which was actually doing a flush (and thus potentially
pushing things the boot ROM wrote into RAM now owned by the OS).
Optimize memory layout a bit when using KERNEL_COHERENCE; we don't
need a full cache line for the start record there as it's already in
uncached memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The multiprocessor entry code here had some bits that look to have
been copied from esp32, including a clumsy stack switch that's needed
there. But it wasn't actually switching the stack at all, which on
this device is pointed at the top of HP-SRAM and can stay there until
the second CPU swaps away into a real thread (this will need to change
once we support >2 CPUS though).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The trace output layer was using this transformation already, make it
an official API. There are other places doing similar logic that can
benefit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Only the CAVS 1.5 linker script has full support for the coherence
features, don't advertise it on the other SoC's yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix kernel.common and kernel.common test cases fail due to build error
in platform intel_adsp_cavs15, 18, 20, 25.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Currently Zephyr links reset-vector.S twice in xtensa builds:
into the bootloader and the main image. It is run at the end
of the boot loader execution and immediately after that again
in the beginning of the main code. This patch adds a
configuration option to select whether to link the file to the
bootloader or to the application. The default is to the
application, as needed e.g. for QEMU, SOF links it to the
bootloader like in native builds.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Looks like those two SoCs still had old header information depending on
Kconfig from SOF, remove those and set trace size directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
LPRAM_BASE and LPRAM_SIZE are duplicates of LP_SRAM_BASE and
LP_SRAM_SIZE respectively. Remove them and use LP_SRAM_*
consistently everywhere.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a
different shim register range, they cannot be accessed, using the
usual SHIM_BASE offset.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
CONFIG_BOOTLOADER_MCUBOOT is never used in cAVS builds, remove
code, supposedly supporting it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
shim.h on cAVS 2.5 contains register definitions, copy-pasted
from other architectures. Fix them to correct values.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
A configuration with CONFIG_MP_NUM_CPUS > 1 and CONFIG_IPM_CAVS_IDC not
defined is valid if COMFIG_SMP is disabled.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Shim register location on cAVS 1.5 is different than on 1.8 and up,
fix it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The current unused memory calculation is broken because it doesn't
take into account the stack area, allocated at the top of HP SRAM.
Until this is fixed disable powering down unused RAM.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
1. SOF doesn't have to be built in .bin format
2. don't include soc.c and soc_mp.c twice in cmake
3. remove an unused mailbox.h header
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On cAVS 1.5, 2.0 and 2.5 platforms the correct manifest address is
0xB0032000.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
rimage dropped its "-m" parameter and switched over to using "-c"
for a configuration file, including a target name.
Add support for extended manifest for all cAVS versions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Unify default configurations to support both SMP and UP:
1. make SMP default, although it's currently disabled in prj.conf
2. use CAVS timer by default in both UP and SMP configurations
3. make MP_NUM_CPUS, IPM and IPM_CAVS_IDC depend on SMP
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The existing implementation of the adsplog.py script worked fine for
individual runs (e.g. when running specific code) but had no support
for detecting system reset events and thus could not be used for
monitoring applications like test automation. It also could not
handle the case where a rapid log burst would overflow the buffer
before being noticed at the client. Also, the protocol here was also
rife with opportunities for race conditions. Fix all that up via what
is mostly a rewrite of the script. The protocol itself hasn't
changed, just the handling.
Also includes some changes to the trace_out.c code on the device side.
These are required to get ordering correct to make race conditions
tractably handleable on the reader side.
Some of the specific cases that are managed:
* There is a 0.4s backoff when a reset is detected. Continuing to
poll the buffer has been observed to hang the device (I'm fairly
sure this is actually a hardware bug, reads aren't visible to the
DSP software).
* The "no magic number" case needs to be reserved for detecting system
reset.
* Slot data must be read BETWEEN two reads of the ID value to detect
the case where the slot gets clobbered while being read.
* The "currently being filled" slot needs to always have an ID value
that does not appear in sequence from the prior slot.
* We need to check the full history in the buffer at each poll to
detect resets, which opens up a race between the read of the "next
slot" (which is absent) and the full history retrieval (when it can
now be present!). Detect that.
* A null termination bug in the current output slot got fixed.
Broadly: this was a huge bear to make work. It sounds like this
should be a simple protocol, but it's not in practice.
Also: clean up the error reporting in the script so it can handle new
PCI IDs being added, and reports permissions failures on the required
sysfs file as a human-readable error.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The toolchain variant per SoC is not always the soc name, so set this
per SoC and use this in the SDK instead of hardcoding the soc name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The fix_elf_addrs script runs objcopy over a binary that (due to some
legacy section definitions in a mildly complicated linker file) has a
few zero-length sections at address zero. Objcopy considers this a
warning condition (though oddly the linker from the same version of
binutils which produced that binary does not!), which will be detected
as a CI failure.
Just eat the warnings. Long term we should rework linkage to remove
the legacy stuff that is getting tripped over.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
SOF uses different SSP clock rates on different cAVS versions. Frequency
tables are provided in platform_ssp_freq[] arrays in clk.c for each
version and the default entry is selected by the SSP_DEFAULT_IDX index.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This section was being put in the wrong region, and was in L1-cached
incoherent memory. That's wrong, as users are expected to expressly
ask for "__incoherent" memory and do manual cache management if
required. Default memory of all types should be uncached and
coherent.
Very few spots use this and cache effects tend to be ephemeral, so it
was somewhat obscure. It was discovered via an SMP race when using
logging very close to system start where the log thread on the second
CPU will race with messages added on the first -- log messages are
stored in a __noinit mem_slab.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This platform had separate backends for the log subsystem and printk
handler, which was silly. Unify them to use the same backend so they
don't clobber each other.
This patch appears to be a lot of lines, but it's really mostly code
motion and renaming.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This IPC protocol is designed to tell the host driver that the audio
firmware is ready. It's not used within the Zephyr in-tree test code,
which does not run under the control of a host driver. And SOF
already does this on its own, the Zephyr attempt to do it first (and
incorrectly) confuses the driver IPC.
Just remove it. This is clearly application code, not platform code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The linker will emit a warning condition when a section with a
declared alignment doesn't naturally start on that alignment (which
begets the question of why the declared alignment syntax exists at
all...).
Do the alignment for .bss between the sections instead as a simple
workaround.
Note that this alignment isn't architecturally required, as current
Zephyr targets don't use the page-aligned pseudo-MMU on this hardware;
the only requirement is alignment to the 64 byte cache stride. It
should work to pack .bss tightly. But when I try that, I get an error
from the rimage tool, which is apparently unprepared for
non-4k-aligned sections?
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a printk default hook that works in very early boot and doesn't
depend on the logging subsystem (which can still be used if desired,
of course). It speaks the same protocol, is somewhat smaller (MUCH
smaller if the app doesn't otherwise need the logging and ring buffer
dependencies), and more efficiently uses the output slot space by
doing line buffering and flushing only when needed.
Most importantly this one is MP-safe via both locking and cache
coherence management, and can work reliably when SMP is enabled.
(Note that "reliable" means that all output appears without corruption
-- simulateous logging by two CPUs can still interleave bytes, of
course).
Longer term, if we keep this protocol it would be good to unify the
two backends to reduce duplicated code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
