Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The compiler shows the array bounds warning message for some boards
which don't set the PSL function.
Change npcx_pinctrl_psl_input_asserted() input parameter from int to
uint32_t to fix it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The low power states 0∕1∕2 are added to the stm32wb.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32wb low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The debug config will let the clocks active in STOP mode
at init.
The substate-id is mapping the same Zephyr power state.
Plus a minor fix in the Kconfig.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power modes are available on the stm32l5 soc
with the mcu STOP0/1/2 modes, depending on the CONFIG_PM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l4.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l4 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Hex firmware file is flashed by default if JLink is used. Since all
of the SiLabs dev boards have an on-board JLink, enable generating hex
file.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
This CL introduces the implementation of configurating PSL input pads
and setting PSL_OUT to inactive level for ultra-low power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
PWR clock is required for various operations.
It is enabled by default in clock control driver,
but disabled at clock init.
It appears soc init is run after clock control driver init
and hence PWR is disabled to to this piece of code at
soc init level.
Don't disable PWR here.
(But keep PWR clock enable in case of ...).
A whole clock clean up will be required later on,
but waiting for that to happen, this is the safest we can do.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This config CPU_CORTEX_M_HAS_DWT, is to avoid the
pragma message "Null-Pointer exception detection cannot
be configured on un-mapped flash areas"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The AN547 is a Soft Macro Model implementation of the SSE-300 subsystem
with Ethos-U55 and Cortex-M55 components targeting the MPS3 board.
The SoC support is based on the AN521 MPS2+ support that already exists
in Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL solves an interrupt storm caused by plenty of host access
messages when system is in S0. It only turns on the host access
interrupt before ec enters sleep and turns it off after leaving
sleep.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add SoC support to enable Cypress PSoC-6 pinctrl. This add devicetree
macros to handle pinctrl nodes and SoC GPIO methods to configure pins.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
CORTEX_M_SYSTICK should be disabled if LPTIM is selected.
Current implementation is not efficient to do so.
Rework the way the dependency is stated.
Fixes#33342
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO driver for QuickLogic EOS S3 SoC.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL prevents changing data content in the write function of host
interface by declaring it as constant pointer.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
All users of ATMEL_SAM0_DT_INST_DMA_NAME are now using
ATMEL_SAM0_DT_INST_DMA_CTLR so we can remove the macro.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a macro similar to ATMEL_SAM0_DT_INST_DMA_NAME but instead
provides the devicetree node back via DT_INST_DMAS_CTLR_BY_NAME
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
SYSCLK_DEFAULT_IOSC_HZ and BUSCLK_DEFAULT_IOSC_HZ are
not used anywhere in the tree and can be removed
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
New power states have more granularity than deep sleep and sleep
states. Just get rid of this and keep the same behavior for now.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Maximum GIC SPI is 228, so maximum INTID is 228 + 32 = 260.
So, _sw_isr_table needs to support 260 entries
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
There is no strict reason to use assembly for the reset routine. Move as
much code as possible to C code using the proper helpers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K2x SoC series.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_PSEL(): get a PSEL value out of the DT from either a
'foo-pin' or a 'foo-gpios' style property.
- NRF_DT_PSEL_CHECK_NOT_BOTH(), NRF_DT_PSEL_CHECK_EXACTLY_ONE():
helpers for checking that a given devicetree is OK according to
different criteria for setting PSEL properties (NAND or XOR on
whether the properties exist, respectively).
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add the declaration and check of debug interface register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ib8ecd53f1d6139613f39243aee83bdd75a30f5be
