We filter out the following kernel tests
- tickless_concept
- timer_api
from the set of tests running on QEMU Cortex-M0 platform,
as the tests consistently fail on QEMU. In addition, we
add a workaround for kernel/interrupt test, so it can
successfully execute on QEMU Cortex-M0.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This is part of the core kernel -> architecture interface
and is appropriately renamed z_arch_is_in_isr().
References from test cases changed to k_is_in_isr().
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit re-works the test for the ARM architecture,
so that it can work with any available NVIC IRQ, not
bound to use the last 2 NVIC lines. It makes use of
the dynamic IRQ feature.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Platforms which use the GEN_SW_ISR mechanism for interrupt handling
can make use of a really simple whitebox trick for verifying that it
worked (i.e. that the pointer and argument get placed in the table
correctly).
Easy and simple way to get some coverage for dynamic IRQs, which is
currently entirely missing. Long term we'll want to replace this with
a test that uses the API directly and chooses an arch-specific vector
to set, and triggers it using arch-specific code, but that's quite a
bit more effort and for now we need to land patches to
z_irq_connect_dynamic() which show test coverage.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
This commit moves the definition of IRQ_LINE(..) macro from
interrupt.h into nested_irq.c, and adds some inline comments
documenting the use of it.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Keeping IRQ0 priority as 1 and IRQ1 priority as 0
so that system timer which of priority 0 in ARC
will be interrupted by IRQ1 of same priority.
In ARM, system timer is of priority 1, hence
making ISR0 priority as 2 and ISR1 priority as 1.
Thus system timer will always be interrupted by
ISR1 in both the architectures.
Fixes: #12147
Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
k_busy_wait() call used in test expects time in us, but the test
is specifying wait in ms.
Also the test fails on NRF5 platform as the test hardcodes the
interrupts priority to 0 and 1 and assumes system timer to be of
priority 0 which is not the case in NRF5 platforms as per
@pizi-nordic where system timer is at priority 1. Hence changing
test interrupts to 1 and 2.
Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
This test was written with an outrageously long timeout of 25 seconds.
That blows right through the 32 bit cycle counter on qemu_cortex_m3[1]
and produces an essentially random delay instead of the desired
number, causing a hang with the new SysTick driver in tickless mode.
Push the number down so it doesn't overflow. The root cause, though,
is that k_busy_wait() can take arguments it can't handle. It ought to
have an outer loop or something so that it can spin for INT_MAX
milliseconds correctly.
[1] Which has a 12MHz clock rate. Many hardware implementations are
much faster still.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This test is intended to verify the interrupt nesting.
Interrupt nesting feature allows an ISR to be preempted
in mid-execution if a higher priority interrupt is signaled.
The lower priority ISR resumes execution once the higher
priority ISR has completed its processing.
Signed-off-by: Ajay Kishore <ajay.kishore@intel.com>
