zephyr

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Author	SHA1	Message	Date
Daniel Leung	f8a909dad1	xtensa: add support for thread local storage Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Note that this does not enable TLS for all Xtensa SoC. This is because Xtensa SoCs are highly configurable so that each SoC can be considered a whole architecture. So TLS needs to be enabled on the SoC level, instead of at the arch level. Signed-off-by: Daniel Leung <daniel.leung@intel.com>	2020-10-24 10:52:00 -07:00
Anas Nashif	9be0f1d251	tests: move xtensa_asm2 tests to tests/arch This is a test, so move it under tests/arch/.. Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2019-09-27 15:23:26 -04:00

Author

SHA1

Message

Date

Daniel Leung

f8a909dad1

xtensa: add support for thread local storage

Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Note that this does not enable TLS for all Xtensa SoC.
This is because Xtensa SoCs are highly configurable
so that each SoC can be considered a whole architecture.
So TLS needs to be enabled on the SoC level, instead of
at the arch level.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

2020-10-24 10:52:00 -07:00

Anas Nashif

9be0f1d251

tests: move xtensa_asm2 tests to tests/arch

This is a test, so move it under tests/arch/..

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

2019-09-27 15:23:26 -04:00

2 Commits