Commit Graph

1496 Commits

Author SHA1 Message Date
Jordan Yates
3894066f79 dts: bindings: zephyr,linker-region property
Introduce optional `zephyr,linker-region` property which signifies that
the node should result in a linker memory region and what the name of
that region should be. Property added to compatibles likely to result
in a linker memory region; 'mmio-sram', 'arm,itcm`, `arm,dtcm`,
`nxp,imx-itcm`, `nxp,imx-dtcm` and `fixed-partitions`.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-12-09 16:23:03 +01:00
Peter Johanson
a5ad94f20f driver: gpio: mcp23xxx: Refactor to generic.
Refactor the mcp230xx driver to generically also support
SPI IO expanders, renaming it to mcp23xxx in the process.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2021-12-08 08:55:28 -05:00
Guillaume Lager
972e5d0274 sensor: eeprom: Add TMP116 EEPROM access
eeprom access is supported by using
either custom or eeprom API

Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
2021-12-08 07:51:46 -06:00
Jay Vasanth
fd43c725d2 drivers: spi: Add MEC172x QMSPI-LDMA driver
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2021-12-08 08:43:05 -05:00
Daniel DeGrasse
cae297d917 drivers: pca9420: added support for current limit setting on PCA9420
Added ability to set VIN current limit when using the pca9420 PMIC

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-08 08:27:44 -05:00
Daniel DeGrasse
130f6eb816 drivers: regulator: add i2c regulator driver
This commit adds a generic i2c regulator driver, and enables the NXP
PCA9420 PMIC IC using this driver. The regulator driver also exposes an
additional API in include/drivers/regulator/consumer.h, which allows
drivers to implement support for adjusting voltage levels and current
limits, if their device supports it.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-08 08:27:44 -05:00
Martí Bolívar
fc2756cf18 dts: nordic: add QSPI XIP area registers for nordic devices
There is currently no information available about the XIP
addresses for the nRF52840 and nRF5340.

Add this via a new 'reg' block in the relevant QSPI nodes, along with
names for the register blocks so they are easier to retrieve.

Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-12-07 20:25:40 -06:00
Pieter De Gendt
4d161a3b23 drivers: counter: NXP SNVS rtc: Add support for NXP imx SNVS RTC
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-12-07 09:45:43 -06:00
Daniel DeGrasse
57f35bbf5a drivers: USDHC: Enable detection using DAT3 pulldown
Enable USDHC host to detect inserted SD card via DAT3 line pulldown.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-06 15:27:25 -05:00
Dominik Ermel
675a113cb4 dts: Add "disk-access" property to fstab bindings
The commit adds "disk-access" property to fstab bindings to allow
selecting FS_MOUNT_FLAG_USE_DISK_ACCESS while defining file
systems in DTS.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2021-12-06 08:08:26 -05:00
Marc Reilly
54b6d26242 drivers: spi: add spi-bitbang driver
This adds an spi master mode driver via bitbanged gpio. Only syncronous
transfers are implemented. Clock signal timing is accomplished via busy
waits, the gpios are manipulated via the standard gpio interface; these
two factors limit the frequency at which it can operate - but here
a simple and generic implementation was chosen over performance.

The driver supports the various clock polarity and phase
configurations, and can also work with word sizes which are non
multiples of 8bits, currently up to 16 bits.

A sample program is also added demonstrating basic use of the driver
with 9bit data words.

Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
2021-12-06 07:29:45 -05:00
Bryce Wilkins
219bf88fe8 drivers: spi: Add optional delays to mcux flexcomm spi driver
Adds optional device tree properties to insert delays between spi chip
select assert/deassert and the clock edges, and also between spi
frames and transfers to the mcux flexcomm spi driver. If the properties
are not set, no additional delay is inserted.

Verified expected behavior on mimxrt685_evk and check with a scope
that the pre- and post-delay could be changed from the device tree
properties.

Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
2021-12-03 16:42:10 -06:00
Hake Huang
f417678e6d dts: bindings: add audio related dts bindings for imx-rt
add anatop, i2s and pinmux dts

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-12-02 10:50:21 +01:00
Antonio Tessarolo
cc1cd4d65b arm: Nxp imx6sx added PWM support
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.

Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
2021-11-30 11:54:11 -06:00
Tomasz Bursztyka
1c1a2ccdbd dts/bindings: Add a dedicated frame format property on SPI device
Most of the time SPI devices use TI's frame format. But some may use
Motorola's. This is already taken care of in the SPI API and now it will
be possible to select the right format from DTS. Like:

    ...
    frame-format = <SPI_FRAME_FORMAT_MOTOROLA>;
    ...

This is only meant to be used for devices supporting both formats (so
the format is not hard-coded in the driver) and selected by hardware
configuration or else.  Which, in such case, it will need to use
DT_INST_PROP(<instance number>, frame-format) macro call to retrieve
the property value. Others can fully ignore it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-29 17:17:36 +01:00
Casper Meijn
85ba056af9 drivers: display: st7789v: Fix software reset
Software reset is already implemented in the driver when the
`reset_gpio` is not defined. However it could not be activated
because the `reset_gpio` is a required field in the DTS
binding.

Signed-off-by: Casper Meijn <casper@meijn.net>
2021-11-29 16:29:33 +01:00
Ruibin Chang
fad78a2c07 ITE drivers/sensor: add tachometer driver for it8xxx2_evb
Add tachometer driver for it8xxx2_evb.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-29 08:25:19 -05:00
Gerard Marull-Paretas
3b7215e160 drivers: serial: nrfx_uarte: add support for pinctrl
This patch adds support for the new pinctrl API to the UARTE driver. The
old pin property based solution is still kept so that users have time to
transition to the new model.

Notes:

- Some build assertions cannot be performed since the driver does not
  have direct access to pin settings anymore. As a result user will not
  be notified if HWFC is enabled but RTS/CTS pins are not configured.
- Hardware flow control can be enabled regardless of pin configuration,
  it is now up to the user to configure RTS/CTS pins in DT.
- Some RX enable checks that were performed using pin information has
  been replaced with a DT property that informs if RX is enabled or not.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 14:20:51 +01:00
Gerard Marull-Paretas
22c8c02145 drivers: pinctrl: nrf: initial support
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.

Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.

Thanks to Marti Bolivar for bindings documentation.

Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 14:20:51 +01:00
Erwan Gouriou
37bf7cbe4f dts/bindings: stm32: Set pinctrl-[0/names] properties as required
Now that STM32 drivers are using pinctrl API, set pintrl-0 and
pintrl-names properties as required in order to report malformed
nodes description soon at build stage and avoid cryptic
DT api build error messages.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
eff3ad6df7 drivers/pwm: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.
Since STM32F1 series require pinctrl option and required register
address is parent timer address in place of own node register address,
use PINCTRL_DT_INST_CUSTOM_REG_DEFINE in place of usual
PINCTRL_DT_INST_DEFINE for this specific series.

Additionally, remove the automatic selection of PINMUX API.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
90b0e92540 drivers/usb/device: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Additionally, rename usb_pinctrl to usb_pcfg to better fit
new pinctrl API.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
8bd410a589 drivers/spi: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ab893d5fef drivers/memc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
79943f647f drivers/i2s: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
f21de9dfe6 drivers/i2c: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
dfbaa4149d boards: arm: stm32: add pinctrl state name for I2C peripheral
Add the pinctrl state name (default) for the I2C peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
cec2cb69dd drivers/flash: qspi stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
87438e4587 drivers/ethernet: stm32_hal: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
d55905b2f7 drivers/disk: sdmmc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
956afc3a08 drivers/dac: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
65d222b0ab drivers/fdcan: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
337c9b96e9 drivers/can: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
93956b2073 drivers/adc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
21a271962c drivers: serial: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Krzysztof Chruscinski
9886bdc0c8 drivers: pwm: pwm_nrf5_sw: Use runtime resources allocation
Use nrfx_gpiote and nrfx_ppi allocators to allocate channels
at runtime instead of fixed, device-tree based allocation which
is harder to maintain.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-11-26 09:31:54 +01:00
Neil Armstrong
3f68124c56 bindings: pcie: add pci-host-ecam-generic bindings
Add bindings for a generic PCIe Controller in ECAM mode.

ECAM stands for PCI Express Enhanced Configuration Access Mechanism
where the PCIe config space is flat memory-mapped.

An optional msi-parent phandle is added to link to an optional
MSI/MSI-X Interrupt Message Translation HW component.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Sam Hurst
cc1cedb82e dts: bindings: Add yaml file for STM32 TCPC support to DT
Add yaml files to DT for initial support of STM32 TypeC
Port Controller (TCPC)

Signed-off-by: Sam Hurst <sbh1187@gmail.com>
2021-11-24 14:21:04 -05:00
HaiLong Yang
5e035b0f4e drivers: serial: gd32 usart add interrupt support
Add interrupt support for gd32 usart driver.

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
2021-11-23 13:25:43 -05:00
Guillaume Lager
4c986a266f drivers: sensor: tmp112: Add default device initialization
This allow to have a smaller driver footprint when a single
configuration is required.

Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
2021-11-23 13:12:39 +01:00
Carlo Caione
983d4606ff ipc_service: Add new RPMsg with static VRINGs backend
Introduce a new RPMsg with static VRINGs backend. This new backend makes
easy to generate and use IPC instances backed by OpenAMP using the DT.

Each instance is defined in the DT as (for example):

  ipc: ipc {
          compatible = "zephyr,ipc-openamp-static-vrings";
          shm = <&sram_ipc0>;
          mboxes = <&mbox 0>, <&mbox 1>;
          mbox-names = "tx", "rx";
          role = "primary";
          status = "okay";
  };

It is then possible to register an send data through endpoints using the
IPC service APIs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-11-22 23:03:23 -05:00
Peter Johanson
d99de305ce dts: bindings: Add generic Xiao interconnect
* With existence of Adafruit Qt Py boards, and upcoming wireless
  Xiao from Seeeduino, define nexus node and peripheral node
  labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
  node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2021-11-22 22:25:20 -05:00
Gerard Marull-Paretas
285f55899b drivers: serial: gd32: use pinctrl
Use the pinctrl API to configure peripheral pins.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
f8017dc5ad drivers: pinctrl: gd32: initial support for AFIO based SoCs
Add a pin control driver for GD32 SoCs using the AFIO model.

Thanks to Gerson Fernando Budke for testing and implementation
suggestions.

Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
543a3843ff drivers: pinctrl: gd32: initial support for AF based SoCs
Add a pin control driver for GD32 SoCs using the AF model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Wealian Liao
5a9bc389f0 driver: gpio: nct38xx: Add NCT38XX gpio driver support
NCT38XX series, which are i2c-based chips, support a different number
of GPIO functionality. For NCT3807, it has 2 GPIO ports on the same i2c
device address. For NCT3808, it has 2 GPIO ports on different i2c
device addresses. This commit adds NCT38XX GPIO driver support &
provides the interrupt handler for the share alert pin.

The following is NCT3807 devicetree node example:
```
&i2c0_0 {
	nct3807_0: nct3807@70 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nuvoton,nct38xx-gpio";
		reg = <0x70>;
		label = "NCT3807_0";

		gpio@0 {
			compatible = "nuvoton,nct38xx-gpio-port";
			reg = <0x0>;
			label = "NCT3807_0_GPIO0";
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin_mask = <0xff>;
			pinmux_mask = <0xf7>;
		};

		gpio@1 {
			compatible = "nuvoton,nct38xx-gpio-port";
			reg = <0x1>;
			label = "NCT3807_0_GPIO1";
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin_mask = <0xff>;
		};
	};
};
```

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-11-20 08:00:38 -05:00
Ruibin Chang
3ab081efe9 ITE drivers/pwm: cleanup it8xxx2 pwm driver
1.Putting the PWM_CHANNEL_X, PWM_PRESCALER_CX information
  in the description.
2.Use the common definition EC_FREQ.
3.Use the common macro IT8XXX2_DT_ALT_ITEMS_LIST.
4.Stop using DRV_CONFIG, DRV_REG macro.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-19 10:24:11 -06:00
Tomasz Bursztyka
4bd5935302 dts/bindings: Add a dedicated property for duplex mode on SPI device
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:

    ...
    duplex = <SPI_HALF_DUPLEX>;
    ....

By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Tomasz Bursztyka
20b8d74d42 dts/bindings: Update HTS221 bindings to enable both i2c and SPI bus
HTS221 is now supported on both buses so let's make DTS aware of it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Gerard Marull-Paretas
1832d68e01 tests: lib: devicetree: add tests for DT_INST_ENUM_IDX(_OR)
Add tests for the instance based enum macros DT_INST_ENUM_IDX and
DT_INST_ENUM_IDX_OR.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-18 19:12:07 -05:00