On Apollo Lake, each GPIO controller has more than 32 pins.
But Zephyr API can only manipulate 32 pins per controller.
So the workaround is to divide each hardware GPIO controller
into 32-pin blocks so each block has a GPIO driver instance.
Compounding to the issue is that there cannot be two device
tree nodes with same register address. So another workaround
is to increment the register addresses by 1 for each block.
So when mapping the address, the lowest 8-bit needs to be
masked to get the actual hardware address.
Fixes#28551
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fixed check condition for GPIO pin number.
This check is done
before reading or writing value for the pin.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
