NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This commit fixes the flash latency calulation in clock_control_init
for stm32wb and stm32wl series:
For these series new_hclk_freq can't be used to set the flash latency,
because the flash clk uses a different prescaler.
Without this fix, the flash latency could be set to an inadequat value
in cases wehere the new AHB3/AHB4 prescaler is different from the
new cpu1 prescler.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds missing initialization of rcc prescalers for
stm32wb and stm32wl series when hse or hsi are selected as
system clock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
stm32wb only has a single msi clock range, in contrast to wl, l4, l5
which have a second range that is active after exit from standby mode.
This difference must be taken account of in the driver.
This commit abstracts __LL_RCC_CALC_MSI_FREQ macro such that all series
can be supported, additionally the switch to the msirange
(LL_RCC_MSI_EnableRangeSelection) is now only executed on series
that support it.
As a result stm32wb socs can use msi as sysclock.
The same should be done for stm32l0, but this commit series limits
the scope of socs to avoid getting too bloated.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commmit restructures the clock_controller code such that the cpu2
prescler assignment later can be excluded for single core socs.
The stm32wl mcu line has variants with a single cortex-m4 core
(stm32wle5), therefore the prescaler for the second clock should
only be set for dual core socs.
This commit still checks for the complete series
(CONFIG_SOC_SERIES_STM32WLX) as the single core variants are not
yet introduced, later the condition should check for a flag like
CONFIG_SOC_STM32WL5X instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes several occurences where a struct members is wrongly
dereferenced, which causes a compile error in case the msi clock is used
as system clock.
Only affects stm32wb and stm32wl with MSI selected as sysclock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In prts of the code, we use rcc node "clocks" property to testify the
use of device tree for clocks configuration.
This doesn't work in case of stm32h7 m4 targets as for those,
"upstream rcc" clock configuration, such as sysclk source selection,
is done on m7 core and hence rcc node doesn't have a "clocks"
property.
To work around this, use alternate "d1cpre" property in case of
stm32h7 targets.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Cortex-M4 stm32mp1 zephyr relies on chip Cortex-A for clock
configuration.
No change is then required for conversion to dts based clocks
configuration, but we do need to exclude use of newly deprecated
Kconfig symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add new symbol CLOCK_CONTROL_STM32_HAS_DTS to exclude definition
of other CLOCK_CONTROL_STM32_* symbols when dts based configuration
is in use.
CLOCK_CONTROL_STM32_HAS_DTS is defined based on availability of
"clocks" property in rcc node.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Symbol CLOCK_STM32_HSE_CLOCK will remain in use in context of stm32
clock_control configuration using device tree, cf commit
a7989f64a3.
In preparation for next change, separate it from the others symbols
definition. Also make it non dependent from other Kconfig symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This is always defined since:
755d09e149 include/drivers/clock_control: stm32: Update for STM32F1
support
So the condition has currently no effect and causes the prescaler to
always be set to /2.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Now that we have specific bindings for STM32F100 devices,
we need dedicated treatment for PLL source HSI case.
Otherwise, we end up using undefined symbol STM32_PLL_PREDIV1.
Please note that previous code compiled, it was assigning
a wrong value to prediv. This had no consequence because
prediv value is forced in Cube LL functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
According to RM0041.pdf clock tree for stm32f100xx devices is
different from both STM32F10X density and connectivity lines devices,
but is a combination of both.
Rework symbols definitions so that STM32F100xx is neither of those
and uses:
- CLOCK_STM32_PLL_MULTIPLIER as on SOC_STM32F10X_DENSITY_DEVICE
- CLOCK_STM32_PLL_PREDIV1 as on SOC_STM32F10X_CONNECTIVITY_LINE_...
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update stm32h7 clock_control driver to make use of macros allowing
dts based configuration in coexistance with existing Kconfig method.
Note: Use of IS_ENABLED is removed as it generates warnings in
checkpatch. This checkpatch behavior needs to be reviewed but may
first require a little clean up of IS_ENABLED macro.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
LL_RCC_HSE_EnableBypass() doesn't exist on stm32wl,
but can be replaced by LL_RCC_HSE_EnableTcxo()
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Kconfig symbol is used in hal_stm32 module to define Cube HAL
symbol HSE_VALUE (cf hal_stm32/stm32cube/CMakeLists.txt).
Due to this specific usage, this symbol should be kept. As a
consequence it could not be replaced by dts equivalent but we can
use dts to configure it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.
MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.
CPG registers allow to get the rate or to set some divider like for
the CAN clock.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Some tools consider this as commented code because of the ifdef, so
remove that and fix a coding guideline violation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The bit RCC_MC_APB3ENSETR_PMBCTRL and RCC_MC_AHB5ENSETR_AXIMC
does not exist in the stm32mp1xx ref manual anymore.
They are not present in the stm32mp1xx_ll_bus.h (v1.4.0).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added support for STM32H753XX by adding CONFIG_SOC_STM32H753XX to list
of H7 SoC with maximum 480MHz SYSCLK.
Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
Remove useless operands since 'bit' field of npcx_clk_cfg structure is
only 3-bit depth and always under 8.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add MCGOUTCLK define to kinetis_mcg.h to make it possible to
use \`<&mcg KINETIS_MCG_OUT_CLK>\` in device tree.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
As this header declares a function that uses a cube defined structure
as argument, it should include the matching header.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added CLOCK_CONTROL_NRF_FORCE_ALT dependency to some options which
are not valid when clock is controlled by out-of-tree driver.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Modified CLOCK_CONTROL_NRF_ACCURACY to represent integer value of
LF clock accuracy.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This will export the stm32_clock_control_init function
to restore the clocks after the low power modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
nRF5340 PDK board was deprecated in v2.5.0 release
and is removed now from the tree.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
With this change it is possible to share all configurations
related to CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION without
including the clock calibration configurations.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Clock calibration should only be used when RC source is used.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
