Add TI VIM (Vectored Interrupt Manager) interrupt controller support.
VIM is a TI specific custom interrupt controller for ARM cores.
In J721E soc, VIM aggregates interrupts to Cortex R5 cores.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
VIM: section 6.3.3.6
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Add fundamental feature support for RP2040 PIO SPI peripherals.
This commit implements synchronous transfer with 8-bit MSB
format. Using PIO allows any GPIO pins to be assigned the roles
of CS, CLK, MOSI, and MISO.
Optional features not implemented yet:
- Interrupt based transfer
- DMA transfer
- Slave mode
- Varying word size
- 3-wire SPI support
- LSB-first
Updated in response to review comments.
Further updates from second round of review.
Rename spi_pico_pio.c source to match zephyr/MAINTAINERS.yml
Remove unnecessary initialization code.
Resolve merge conflicts
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
As per #26393, Local APIC is using Kconfig based option for
the base address. This patch adds DTS binding support in the driver,
just like its conunter part I/O APIC.
Signed-off-by: Umar Nisar <umar.nisar@intel.com>
Add missing definitions for ALH DAIs. Keep the same FIXME
reminder in the comments we have for ACE1.5 that explains
the background of these definitions.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
i.MX RT SoC have some pins related to the watchdog.
For example, iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb allows WDOG1_RST_B_DEB
signal to be used as reset source for i.MX RT10xx boards.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
Update SNVS pin names in RT11xx DTSI files to align with new pin data
generated for the RT1176 and RT1166 processors. This pin data is stored
within the NXP HAL, so the SHA of the HAL is also updated by this
commit.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
To properly setup L1 exit timing this patch will use buffer interrupt
for HOST DMA and wait for Host HDA to actually start
First interrupt will clear all others.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Davinci gpio controller support to add various soc gpio
support (J721E, AM654).
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
GPIO: section 12.1.2
BeagleBone AI_64 https://beagleboard.org/ai-64
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Created a seperate device tree file for the stm32f765.
Moved common nodes from the stm32f767 device tree file to the new file and
based the stm32f767 off the stm32f765.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Allow use of multiple mb85rc frams at contiguous i2c addresses as a single
big fram module.
Tested on mb85rc1mt used as two 32K modules, where the first one was at
mb85rc1mt's first i2c address and the second one at mb85rc1mt's second i2c
address.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
The added cellular modem driver is a naive driver, which
shall serve as a template for implementing tailored
drivers for modems like the UBLOX-R4. It uses only
generic at commands, described in 3gpp, and protocols,
like CMUX and PPP.
A binding for the BG95 has been added, which replaces
the quectel,bg9x. This is neccesary since the BG95 does
not have a usable reset pin, the reset and powerkey are
internally connected to each other.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
The current-shunt calibration requires a factor of 4x if high-precision
mode is selected.
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
STM32L1, U5 and WBA can only have an asynchronous clock source for ADC.
STM32F2, F4 and F7 can only have a synchronous clock source for ADC.
For all these series, it can be defined directly in the dtsi files.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add two properties to define the STM32 ADC clock source:
- Clock source: synchronous or asynchronous
- Clock prescaler
By combining these two parameters, it will be possible to set the desired
ADC clock for most series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a pseudo device which can be used to hook into gpio-keys input_events
and relay the events to a lv_indev.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add the scaffolding to create input lvgl pseudo devices which route zephyr
input_event to their lvgl `indev` equivalent. As a first cut also add a
`zephyr,lvgl-pointer-input compatible which can be a drop-in replacement
for the existing kscan solution.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
This commit changes the I2C instance to IOM.
IOM instance can be I2C or SPI. The choice of either
using I2C or SPI should be made in board DTS.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Added configuration of termination current and trickle voltage
Added option to bypass low voltage charge inhibit
Added option to disable automatic recharge
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
/delete-node/ pointing at node labels needs to be out of the the tree
hierarchy, fixes the error:
devicetree error: zephyr/dts/arm/nordic/nrf52840_qfaa.dtsi:24 (column
16): parse error: expected node name
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
AXP192 is a small power management IC, that also
features 5 GPIOS.
Besides GPIO driver this commit also includes needed modifications
in axp192 regulator and mfd driver as LDOIO0 functioanlity
is multiplexed with GPIO0 pin.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Many fuel gauge ICs offer a battery cutoff/shipping mode functionality that
cutoff charge from the battery. This is often useful for preserving battery
charge on devices while in storage.
Add battery cutoff support to the fuel gauge API with a generic default SBS
driver showing an example of support in tests.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
This adds QSPI controller properties that allow tuning
chip select timings (needed for accessing QSPI at high speed)
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
RC32K/RCX/XTAL32K were present in device tree as fixed-clock.
Now calibration time for RCX and RC32K is added and settle time
for XTAL32K so additional binding is created.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
