The default S0S1 drive setting is not suitable for TWI/TWIM pins.
Override it with S0D1 as for some SoCs (e.g. nRF52833) without
this the peripheral will not work properly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix indentations of `adc_stm32_oversampling` function comments
to have everything aligned properly.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
According to the ES0418 about the ADC of the stm32G071
or other stm32g0x devices:
for sampling time set to 1.5 or 3.5 cycles,
the sampling in a single ADC conversion or in the first
conversion of a sequence takes one extra cycle.
Minimizing to 7.5 is fine.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- If the HAL headers expose the USBPRE flag, then we're probably
dealing with a F103 - using the same fundamental logic as the
code for the OTG models, set-up the USB Prescaler correctly.
- Fixes#47146
Signed-off-by: Chris Collins <chris@realsimgear.com>
TCA954X driver was not enabled since introduction of
new compatibility fields.
We now set I2C_TCA954X depending on related "okay"
compat fields in DT.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
After replacing STM32_SRC_PLLCLK by the STM32_SRC_PLL_x sources
this function is no longer needed and are therefore removed.
Also, those functions returned a wrong frequency.
They should have used get_pllsrc_frequency() instead of get_pll_source()
to get the input frequency.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The SOC specific implementations of the clock_stm32_ll_common driver
included the PLL specific functions only when PLL was selected as sysclock.
This commit changes the condition from "STM32_SYSCLK_SRC_PLL"
to "defined(STM32_PLL_ENABLED)".
As a result the pll could also be used as peripheral clock source
in case it is not the sysclock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds support to select pll outputs as peripheral clock
sources to the stm32 common driver.
With this commit they are only available on
STM32G0, STM32G4, STM32L4, STM32L5, STM32WB, and STM32WL.
Support for STM32F2, and STM32F4, which also have p,q,r dividers,
is not enabled in this commit.
Also, stm32_clock_control_get_subsys_rate is extended to return
the configured frequency in case they are enabled, otherwise 0.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit configures the PLL_P divider for SOCs compatible to the
stm32_ll_common driver in case a value was defined via a dts property.
Additionally, in case the divider value is defined in the device
tree, the respective pll output is enabled during initialization
in set_up_plls().
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In the stm32_ll_common driver the PLL_Q divider should not
be directly written to RCC->PLLCFGR->PLLQ, but should be
translated to the matching register value.
i.e. shifting the value to the correct position of the register
is not enough.
This commit makes sure the divider value taken from device tree, is
correctly translated ot the matching register register value by
converting it to a STM32CUBE LL definition LL_RCC_PLLQ_DIV_xx.
Typcial divider to register value mapping:
G0, WB, WL:
Dividers 2-8 mapped to register values 1-7(0 reserved).
G4, L4, L5:
Dividers 2,4,6,8 mapped to reg values 0,1,2,3.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
All these series share the same defines, and while they are not used
by all socs of the common-driver, this is not exptectd to lead to
any conflict.
By moving the defines they can also be used in clock_stm32_ll_common.c
Additionally, the stm32g0 pll_div define was renamed to pllm
in order to match the other series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The STM32_SRC_CLOCK_MIN and STM32_SRC_CLOCK_MAX defines
are not really needed because non valid clock sources are already
filtered out by the precompiler.
Only STM32_SRC_CLOCK_MIN was used once in code and can be replaced.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes a bug where an already received Rx frame could not be
processed by the IEEE 802.15.4 driver.
In the current implementation, buffer is marked as free and released to
the buffer pool after `nrf_802154_buffer_free_raw` finishes executing.
However, delays caused by thread scheduling might result in a new frame
being already received and provided to the driver before
`nrf_802154_buffer_free_raw` returns. Such a situation ends in an
assertion now.
This commit changes that behavior by marking the buffer as free before
calling `nrf_802154_buffer_free_raw`.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
This commit increases verbosity of serialization error handler for
nRF5340 application core. The handler prints the error code now.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
As we work to phase out devicetree 'label properties, convert
driver to just use dev->name instead of DT_INST_LABEL.
Signed-off-by: Kumar Gala <galak@kernel.org>
