add CAN_1 and CAN_2 hw modules support
Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
AArch64 has support for PSCI. This is especially useful for SMP because
PSCI is used to power on the secordary cores.
When the PSCI driver was introduced in Zephyr it was designed to rely on
a very PSCI-centric subsystem / interface.
There are two kinds of problems with this choice:
1. PSCI is only defined for the non-secure world and it is designed to
boot CPU cores into non-secure state (that means that PSCI is only
supposed to work if Zephyr is running in non-secure state)
2. There can be other ways or standards used to start / stop a core
different from PSCI
This patch is trying to fix the original wrong assumption by making the
interface / subsystem a generic one, called 'pm_cpu_ops', and using PSCI
only as an actual driver that is a user of this new interface /
subsystem.
For now the new subsystem is only exposing two methods: cpu_on and
cpu_off, others will probably follow according to the needs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The DMA bindings had duplicate description: keys. Merge the two
descriptions into one to fix the issue.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Many data items that are represented in a pin configuration node are
common and generic. Pin control bindings should use the properties
defined on a standard way when are applicable; not all of these
properties are relevant or useful for all hardware or binding
structures. Each individual binding document should state which of
these generic properties, if any, are used, and the structure of the
DT nodes that contain these properties.
This is based on Linux, documentation:
https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K2x series.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Conver the NIOS-II mSGDMA driver to be devicetree based. Add node for
dma controller into nios2f.dtsi.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Deprecate the scl-pin and sda-pin properties in the devicetree.
Provide new scl-gpios and sda-gpios properties instead.
This lets the user specify SCL and SDA like this:
&i2c0 {
scl-gpios = <&gpio0 1 0>;
sda-gpios = <&gpio1 4 0>;
};
Instead of having to use:
&i2c0 {
scl-pin = <1>;
sda-pin = <36>;
};
Provide error checking and understandable error messages for invalid
configurations.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Convert ism330dhcx INT_PIN attribute from Kconfigs to Device
Tree binding properties. Here int-pin has been defined as
enum with two possible values: 1 and 2.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Convert ism330dhcx accel and gyro odr attributes from Kconfigs to Device
Tree binding properties.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Converts ism330dhcx accel and gyro range attributes from Kconfigs to
Device Tree binding properties.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Create a common properties file that will be included by all bindings
(as i2c and spi) handled by ism330dhcx driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The wifi controller isn't accessed via MMIO and thus shouldn't
exist under the SoC node which is for MMIO based devices so move
it up a level.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Change dfe-ant-num propert name to dfe-antenna-num.
The change is conde to keep the same naming style
for all properies, like dfe-pdu-antenna property.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Add initialization of GPIOs that are used for antenna switching.
GPIOs provided to DFE extension in Radio peripheral, to drive
antenna switching, should be initialized in GPIO peripheral beforehand.
The initialization is optional and may be disabled by Kconfig.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Add quadspi node in stm32f7.dtsi and quadspi support to boards
stm32f746g_disco and stm32f769i_disco.
Note! Does not support DMA.
Signed-off-by: Helge Juul <helge@fastmail.com>
NPCX chip allows firmware to select the JTAG0/1 via bit 2/1 in the
DEVALT5 register. However, the selection logic is reverse
(i.e. 0:select; 1:not select.)
This change fixes the wrong setting of the invert field.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I2c080feaa7647e940463d9491b61a342c84a6141
The size of System Configuration register cannot exceed 0x70. Otherwise,
it will overlap the Debug Interface register which starts from
0x400c3074.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Modifications to incorporate latest write to new flash area
Modification to avoid writing garbage to new flash area when compactor
is called during init.
Modifications to allow erase at partition size instead of eeprom
pagesize.
Modifications to better separate rambuf usage from flash usage.
Corrected some errors in compactor
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This driver emulates a EEPROM device in flash.
Reworked implementation with modified flash layout.
The emulation represents the EEPROM in flash as a region that is a
direct map of the eeprom data followed by a region where changes to
the eeprom data is stored. Changes are written as address-data
combinations. The size of such a combination is determined by the
flash write block size and the size of the eeprom (required address
space), with a minimum of 4 byte.
The eeprom page needs to be a multiple of the flash page. Multiple
eeprom pages is also so supported and increases the number of writes
that can be performed.
The eeprom size, pagesize and the flash partition used for the eeprom
are defined in the dts. The flash partition should allow at least two
eeprom pages. For fast read access a rambuffer can be enabled for the
eeprom (by setting the option rambuf in the dts).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
Add device tree nodes for QDEC peripheral instances
for nRF5340 Application core.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
