What is the changed?
CPU affinity test for SMP cores will now cover a change in ROM offset.
How is it changed?
Add a new testcase section with ROM offset set to something other than
the default 0.
Why is it change?
There is no test to cover the issue reported in #76182 and the cpu
affinity test is the closest to test the issue. Adding a new testcase
will makes sure there is no breaking change in the future.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add dedicated interrupt lines for nrf54h20_cpuppr. Similar exception
was already added to nrf54l15_flpr: 8742e2476.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This needs special treatment because the TEST_MEM_MAP section
is placed at the end. Since there is code in TEST_MEM_MAP,
rimage thinks the whole text section spans from .text to
end of TEST_MEM_MAP, which overlaps .data and others, so
it complains. Skip the execution test to avoid this issue.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The board has been renamed from intel_adsp/ace30_ptl to
intel_adsp/ace30/ptl. So the corresponding board only configs
for tests also need to renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Unlike a normal IRQ, a multilevel IRQ can't be incremented by
simply `irq++`, as that would always increment the L1 of a IRQ,
regardless of its level. A function that understands the level
for which the IRQ operates in is required.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Test multilevel-irq APIs with interrupt number generated from
the devicetree to make sure that they work in sync.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The following Kconfigs are always enabled on `qemu_riscv32`:
- CONFIG_MULTI_LEVEL_INTERRUPTS
- CONFIG_2ND_LEVEL_INTERRUPTS
- CONFIG_RISCV_PRIVILEGED
No need to enable/filter for them in the testcase.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The multilevel IRQ APIs tests are currently cordoned off by
`CONFIG_MULTI_LEVEL_INTERRUPTS` compiler switch, do this more
cleanly by moving it to another file and use cmake for that
instead.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The IRQ for level 1 and above is incremented by 1 when encoded
with Zephyr's multilevel IRQ scheme, so it should be
decremented by 1.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This is in preparation for adding another SoC where qemu_xtensa
is no longer valid choice. So use qemu_xtensa/dc233c as it is
the same as the old qemu_xtensa.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Current clocks configuration for the platform makes it impossible
to pass the IDLE_EVENT_STATS_PRECISION check. This is to be addressed
in the future.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
This case fails to build on boards having APIC TSC timer enabled.
This change is needed after moving APIC TSC timer support from
apic_timer.c to apic_tsc.c.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Up until now, the `__thread` keyword has been used for declaring
variables as Thread local storage. However, `__thread` is a GNU
specific keyword which thus limits compatibility with other
toolchains (for instance IAR).
This PR intoduces a new macro `Z_THREAD_LOCAL` which expands to the
corresponding C11, C23 or C++11 standard keyword based on the standard
that is specified during compilation, else it uses the old `__thread`
keyword.
Signed-off-by: Daniel Flodin <daniel.flodin@iar.com>
For code clarity, remove unnecessary `return` statements
in functions with a void return type they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit re-enables the following platforms for the
`kernel.common.stack_sentinel` test:
* `hifive1`
* `m2gl025_miv`
These platforms working correctly after Renode was upgraded to 1.15.2 in
the CI.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Few tests with wrongly names platforms. This section is now being
verified for correctness like all others.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the
devicetree
- Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to
be able to encode the L2 IRQs.
- Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024)
Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase
accordingly, so that it won't overflow the configured bits.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit excludes the `m2gl025_miv` platform from running the
`kernel.common.stack_sentinel` test. It experiences the same issue as
`hifive1`, which was described in issue #66070.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This provides memory mappings with the ability to be initialized in their
paged-out state and be paged in on demand. This is especially nice for
anonymous memory mappings as they no longer have to allocate all memory
at mem_map time. This also allows for file mappings to be implemented by
simply providing backing store location tokens.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
An ifdef should have been also checking for native_sim,
let's correct it.
Note: By now native_sim builds with "native_posix compatibility mode"
enabled, which sets BOARD_NATIVE_POSIX to avoid breaking all this kind
of dependencies. But that will stop soon.
So let's fix the dependencies.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a zephyr/printk.h header for the __printk_hook functions, these are
currently manually declared by all console drivers for no good reason.
Move the documentation into the header and also unify the way that
console drivers call the function.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Like in C test. If MAX STDDEV is lower than single clock cycle then
set it to a single clock cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
If frequency of the system clock is lower then deviation may exceed
default value (10us). Instead of adjusting the default value, test is
rounding up expected standard deviation to a single clock cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
`checkpatch.pl` requires that dts sources are indented with tabs,
fix all the spaces that slipped in while checkpatch wasn't watching.
Signed-off-by: Jordan Yates <jordan@embeint.com>
When content validation fails it is rather difficult to figure out the
cause if some meaningless byte mismatches another meaningless byte.
Let's store each memory location with its own virtual address so if a
mismatch occurs when reading it back it is obvious where it comes from.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Make sure constructors are run even when not using C++.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Adds a test to show that enabling IPI cascades
(CONFIG_SCHED_IPI_CASCADE=y) can correct an invalid set
of high priority threads on an N CPU system.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Add the ability to touch memory in the opposite direction from one loop
to the next so to exercize the LRU eviction algorithm.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This patch file updates the use of assertion macros
comparing strings.
Command line used:
```
./scripts/coccicheck --mode=patch \
--cocci=scripts/coccinelle/ztest_strcmp.cocci tests/
```
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
