Fix build of nrf_qspi_nor flash driver without multithreading enabled.
This is required for builds like mcuboot.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
IAP is a reference to the method of software interaction with the flash
used in the current driver implementing support for this flash. The
DT compatible should not be named like this.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a flash copy command, capable of copying a region in one
flash device to a region on the same or another flash device. The
destination is erased prior to copying.
This is useful for evaluating mcuboot on devices with little
on-chip resources, or devices that are incapable of running more
elaborate image management services (e.g. via bluetooth or
networking).
Additionally, it's useful for evaluating mcuboot on devices with
one or more images stored on external spi flash.
The command syntax is
flash copy <src_dev> <dst_dev> <src_offs> <dest_offs> <size>
E.g.
flash copy flash@0 flash-controller@abcd1234 0x1234 0x5678 21012
Copied 21012 bytes from flash@0:1234 to \
flash-controller@abcd1234:5678
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Provide a generic flash_copy() algorithm that is capable of
copying from one flash device to another or within different
regions of the same flash device.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
The flash simulator assumes that flash is being addressed with absolute
addresses by clients. But this is not the case. Given addresses are
relative to the flash base address.
The existing code only worked because the base address was always zero.
Testing with non-zero base addresses caused a mem fault/page fault.
(Reproducible e.g. when using the NVS settings subsystem on QEMU x86
with a non-zero base address in the soc-nv-flash node.)
Fixes#79082
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add the write_unprotect command to the stm32 qspi flash driver
to un protect flash before any write operation to the external quad-NOR
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the support of the requires_ulbpr property when a Microchip
quad-spi flash is mounted.
Set the CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32=y flag to access
the command
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Some applications may require the SPI NOR driver to be initialized
earlier. This commit enables the user to change the default
initialization priority.
Signed-off-by: Vidar Berg <vidar.berg@nordicsemi.no>
The CONFIG_PINCTRL setting is removed from the board
_defconfig files. And "select PINCTRL" is added to
the appropriate driver files.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Currently, if we try to write data from a memory mapped flash address
to the flash then we get a -EINVAL error.
This could break the settings subsystem when we use NVS backend.
In order to make it work, add a buffer and use it when we want to
write data that is located in flash address space.
This has been tested using sample/subsys/settings/
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Correct used lines based on write opcode
regardless of the data mode.
The write opcode is set during init for all
modes and can be overwritten in DT.
Add lines correction for PP_1_1_2.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds a basic driver for the STM32WB0 flash controller (read/erase/write).
Extended operations are not supported by this driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add condition for KConfig Renesas FSP hal module
Move the DUAL_BANK_MODE from SOC to flash driver KCONFIG
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Wait until the erase operation triggered by `qspi_erase` completes
before returning. This aligns with the behaviour of other flash drivers
like `spi_nor` and `soc_flash_nrf`.
A delay is added to the `qspi_wait_while_writing` to prevent the check
from monopolising the CPU.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Move some STM32 drivers related Kconfig symbols from `config`
to `menuconfig` when driver options depends on these symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Select PINCTRL subsystem by drivers which require it.
Prevent the need from enabling this symbol at board or soc level.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Automatically handle device runtime PM for all flash API calls.
Asynchronously release the device after a small delay to minimise power
state transitions under multiple sequential API calls (e.g. NVS).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Remove `SPI_NOR_IDLE_IN_DPD` to simplify the possible transition states
in the `spi_nor` driver. This option was originally added 5 years ago
when device runtime PM was in a much less mature state.
I do not believe having a separate power management implementation for
this one in-tree driver is in the interests of the project.
The behaviour of `SPI_NOR_IDLE_IN_DPD` leads to extremly suboptimal
behaviour in use cases where multiple small reads are performed
sequentially, see #69588.
Removal of this option does not break the behaviour of any existing
applications, only increases current consumption in idle by ~10uA until
device runtime PM is enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Can be used only once the SiM3U SoC support has been added.
Developed-by: Michael Zimmermann
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Some flash/memc drivers like flexspi will want to default the
value of the log level to off to avoid RWW hazard while XIP,
to do this, the logging template must be sourced after the driver
kconfig files so that the default value from the driver is able
to be checked, since logging template introduces an unconditional
default otherwise.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Use the define to send the reset cmd at quad-flash init :
SPI_NOR_CMD_RESET_EN followed by SPI_NOR_CMD_RESET_MEM
when the st,stm32-qspi-nor has the <reset-cmd> property set.
Reports the jedecID correctly.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove dead code. The write opcode instruction
is set based on dev_data a couple of lines after.
This was supposed to be in the merged "memory map
support for other modes" PR.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
When application code runs from M4 (resides on lower 896KiB of
the internal flash of bank2) and it does write to a block in
the upper 128KiB, write fails sometime (for example failed
1 out of 10 block write based on the tests) due to STRBERR.
As per technical reference manual section 4.7.4 of
STM32H745/755 SoC, application may ignore this error and
continue with write. So check for the flag and return okay
status for write(). Based on our tests, the application write
succeeds even when this error happens and match with document
description. So igoring this error flag is okay during write.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Add more clarity to memory map log output.
Use LOG_DBG instead of LOG_INF to signal about
memory map mode being enabled.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
REG_X_BASEADDR will be removed from all hal files.
This forces the use of the peripheral base address
Define MSPI_PORT macro for chip drivers
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
RRAMC peripheral is a secure-only peripheral, and the application
cannot use it directly. While building an application with TF-M
enabled and SOC_FLASH_NRF_RRAM the NRFX_RRAMC selection must
be forbidden.
Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
This variable is only used under DUAL_BANK condition and a warning
is generated in !DUAL_BANK case, so move its definition accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
When QSPI configuration is the dual-flash, the total
flash size and erase size are doubled. This is handled
with a STM32_QSPI_DOUBLE_FLASH factor which doubles
the values of one qspi component.
Note that SFDP table is for ONE flash component.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The offset is wrong when the second bank is used by M4 as the
offset is relative to the base which is 0. So add the least
significant 6 nibbles from the CONFIG_FLASH_BASE_ADDRESS to
find the sector.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Currently flash controller driver builds and runs only on M7.
This patch supports enablement of the driver on M4 CPUs. The
main issue in using the driver on M4 is that LL_GetFlashSize()
to read the flash size works only on M7 as the internal register
is not accessible from M4. So to use the driver on M4, add a dt
property, bank2-flash-size, to configure flash size of bank2.
this will allow gradual support of flash controller driver
on M4 of all supported STMH7 boards by defining the above
dt property and testing it. Currently this is verified only
on STM32H747i-disco board.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
