The Arduino 101 comes with a bootloader that supports DFU
and flashing of all cores using the dfu-util package.
This changes the memory layout of the image built for the
Arduino 101 and remove previous work-arounds to allow booting,
including the version-header section in the linker script.
The bootloader expects the text section at +0x30 from the physical
load address and thus requires special treatment in the linker
script.
Other changes by Andrew Boie:
The flash size parameters were both wrong. X86 side has 192K
of flash from 0x4003000 - 0x40060000, the entire span of
sys_flash1.
ARC side is now the span from 0x40010000 - 0x40030000, 128K.
Change-Id: Iecfa5d2b84a3f522d9eca06268d6b8b71a094aaa
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In 1.0 you could set only one callback on the whole gpio controller. It
was impossible for another sub-system to add another callback, without
overwritting an existing one.
Such API has been obsolete for a long time and no one is using it
anymore. Thus removing it entirely.
Change-Id: I6a17fd99373dc6cef1fa2ebb421e992412d5015e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The x86 architecture port is fitted with support for the unified kernel,
namely:
- the interrupt exit code now calls _Swap() if the current
thread is not a coop thread and if the scheduler is not locked
- there is no 'task' fields in the _nanokernel anymore: _Swap()
now calls _get_next_ready_thread instead
- the _nanokernel.fiber field is replaced by a more sophisticated
ready_q, based on the microkernel's priority-bitmap-based one
- nano_private includes nano_internal.h from the unified directory
- the FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
priority drives the behaviour
- the tcs uses a dlist for queuing in both ready and wait queues instead
of a custom singly-linked list
- other new fields in the tcs include a schedule-lock count, a
back-pointer to init data (when the task is static) and a pointer to
swap data, needed when a thread pending on _Swap() must be passed more
then just one value (e.g. k_stack_pop() needs an error code and data)
- fiberRtnValueSet() is aliased to _set_thread_return_value since it
also operates on preempt threads now
- _set_thread_return_value_with_data() sets the swap_data field in
addition to a return value from _Swap()
- convenience aliases are created for shorter names:
- _current is defined as _nanokernel.current
- _ready_q is defined as _nanokernel.ready_q
- _Swap() sets the threads's return code to -EAGAIN before swapping out
to prevent timeouts to have to set it (solves hard issues in some
kernel objects).
- Floating point support.
Note that, in _Swap(), the register holding the thread to be swapped in has
been changed from %ecx to %eax in both the legacy kernel and the unified kernel
to take advantage of the fact that the return value of _get_next_ready_thread()
is stored in %eax, and this avoids moving it to %ecx.
Work by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Allan Stephens <allan.stephens@windriver.com>
Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: I4ce2bd47bcdc62034c669b5e889fc0f29480c43b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Commit 3e63a74514 did not revert properly
things.
Change-Id: I792d5698966542ce2cfb9f858c56b30c392f02a2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
You can't query the LOAPIC for every kind of interrupt that fires,
it has no idea about IRQs that were generated by an 'int' instruction
for example. Extend the semantics of _irq_controller_isr_vector_get()
to return -1 if the vector can't be identified.
Issue: ZEP-602
Change-Id: I1174aa62fbedffdcd329d60da8ef14fabb042dc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These files were almost exactly the same and had already started
bit-rotting (note the missing net_l2 section in linker_harvard.ld)
Issue: ZEP-528
Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This reverts commit d73a9bb9c6.
The patch was intended for 1.6.0 release.
Change-Id: Id42058b746a3d2a54e4b1a2983eb58bd10b1ed40
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:
_EXCEPTION_CONNECT_CODE(handler, vector)
_EXCEPTION_CONNECT_NOCODE(handler, vector)
For x86 exceptions that do and do not push error codes onto
the stack respectively.
In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c
Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.
CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.
Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rather than embedding the ISR stub directly inside the function that
invokes IRQ_CONNECT(), stick all the generated stubs in the
.text.irqstubs section.
In this way, we make things easier to debug since the stub code isn't
mixed in with the "calling" function's assembly, and we no longer
need an instruction to jump over it.
Since these are now in their own section and not embedded inside an
unrelated init function, we unconditionally generate descriptive
symbol names for each stub based on the name of the handler and the
IRQ line.
Example for HPET timer on IRQ #2:
00100440 T _timer_int_handler <-- driver ISR
00100590 T _timer_int_handler_irq2_stub <-- generated stub
Change-Id: I49425aef7775edbca8ad7f61d2d4f9c41cb0d39d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Follow up to TSC decission for further discussion in the networking
WIG.
Change-Id: I148b484dfe308661573e47ed3e60cceed673bddf
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Nios II appears to have an issue with the 'stbio' instruction.
When executing this code:
0x00400848 <+136>: stbio r3,0(r2)
With these registers:
r2 0x44000c 4456460
r3 0x3 3
The memory location (which is a memory-mapped register in the
NS16550 IP block) ends up with the value 0x103 instead of 0x3 as
expected. Before the instruction ran, the register had 0 in it.
32-bit version doesn't seem to have this problem, use that
everywhere for now. This issue has been reported to Altera.
Change-Id: I4ff0ff4cc7f9b18006d3f7a777eb292924843644
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having two parallel implementations is a maintenance issue, especially
when some strategically placed #ifdefs will suffice.
We prefer the ASM versions for SYS V, as we need complete control of
the emitted assembly for interrupt handling and context switching.
The SYS V code is far more mature. IAMCU C code has known issues with
-fomit-frame-pointer.
The only difference between the two calling conventions is that the
first three function arguments are provided in eax, edx, ecx instead
of on the stack.
Issue: ZEP-49
Change-Id: I9245e4b0ffbeb6d890a4f08bc8a3a49faa6d8e7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Net core then does not know anything about l2 related logic.
For instance ARP is used in ethernet l2 API and nowhere else.
This will be helpful when adding different technologies altogether.
Currently, only SLIP driver is enabled to use relevant l2 layer.
Change-Id: I03c93326321028d04222733ca4083e3c6b785202
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will be used by the new network stack to relate a device to actual
network context, and used in the different layers (mac, ip ...).
Change-Id: I30c08fa975314544c36b71636fd9653d562891b3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now allow use of -mgpopt=global and -mgpopt=data. The 'global'
option is now the default instead of compiler-default local, expanding
global pointer usage to all small data in the system.
For systems where all RAM is less than 64K, the 'data' option may be
appropriate.
Some fixes had to be made to the system in order to get around some
issues:
* prep_c.c no longer uses fake linker variables to figure out the size
of data or BSS, as these gave the linker fits as it tried to compute
relative addresses to them.
* _k_task_ptr_idle is create by sysgen and placed in a special section.
Any small data in a special section needs to be declared extern
with __attribute__((section)) else the compiler will assume it's in
.sdata.
* same situation with extern references to k_pipe_t (fixed pipe_priv
test)
For legacy applications being ported to Nios II which do things that
freak out global pointer calculation, it can be disabled entirely.
Change-Id: I5eb86ee8aefb8e2fac49c5cdd104ee19cea23f6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
needs to be 0x8000 after .sdata and .sbss sections since
register offsets are 16-bit signed values.
Change-Id: Ia7486d32af81e54a6ebac6be7ec308dfdeafe79e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The caches get initialized on boot and flushed after XIP copy
takes place.
Change-Id: I642a14232835a0cf41e007860f5cdb8a2ade1f50
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Updates the exception stack frame structure to include floating point
registers.
Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We are not going to handle unimplemented math instruction
exceptions at runtime. Remove remaining comments and exports
related to this. We don't need to leave a gap in the exception
stack frame for it either.
Change-Id: I4f1f3980a0e43bbf6f2f7488a9182f7acb06be05
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are no-ops since this is not an arch that isn't byte-
addressable.
Change-Id: I09b0fd8b8d85f67bcca2dcb6ebc35843c19afa45
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.
Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The technical manuals and example HAL code frequently refer to
register bank numbers from some base address. Add these helper
functions to read and write registers correctly using this
notation.
Change-Id: Ia082f5cc89081fcea2cb6ad8204c1b9b2650d3fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The KEEP() is only necessary for the exception entry point
as it sits at a magic memory address and isn't referenced by
other code.
Change-Id: I8443e8aa23059b65eaf9c5a1cf3f9b14b04737d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This isn't directly referenced by other code in the binary,
it just sits at a magic memory address. Make sure gc-sections
doesn't throw it away.
Change-Id: I1c00a163dbf2eb4866ebadc7f1d70bcc6845b8d1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These aren't valid in all circumstances; the reset vector in most cases
needs to be in ROM.
Change-Id: I83df8762eecc53c99af92f3b0972dfbafac457fb
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The problem is doxygen's parser is getting confused by constructs as:
static inline __attribute__((always_inline))
void sys_out8(uint8_t data, io_port_t port)
{
_arc_v2_aux_reg_write(port, data);
}
Too many words at the beginning of the function definition. So change
to use the macro ALWAYS_INLINE (which is already defined to mean
'inline __attribute__((always_inline))`.
Kills:
sys_io.h:37: warning: documented symbol `static inline void sys_out8' was not declared or defined.
sys_io.h:47: warning: documented symbol `static inline uint8_t sys_in8' was not declared or defined.
sys_io.h:58: warning: documented symbol `static inline void sys_out16' was not declared or defined.
sys_io.h:68: warning: documented symbol `static inline uint16_t sys_in16' was not declared or defined.
sys_io.h:79: warning: documented symbol `static inline void sys_out32' was not declared or defined.
sys_io.h:89: warning: documented symbol `static inline uint32_t sys_in32' was not declared or defined.
sys_io.h:120: warning: documented symbol `static inline int sys_io_test_bit' was not declared or defined.
sys_io.h:133: warning: documented symbol `static inline int sys_io_test_and_set_bit' was not declared or defined.
sys_io.h:146: warning: documented symbol `static inline int sys_io_test_and_clear_bit' was not declared or defined.
sys_io.h:161: warning: documented symbol `static inline void sys_write8' was not declared or defined.
sys_io.h:171: warning: documented symbol `static inline uint8_t sys_read8' was not declared or defined.
sys_io.h:182: warning: documented symbol `static inline void sys_write16' was not declared or defined.
sys_io.h:192: warning: documented symbol `static inline uint16_t sys_read16' was not declared or defined.
sys_io.h:248: warning: documented symbol `static inline int sys_test_bit' was not declared or defined.
sys_io.h:261: warning: documented symbol `static inline int sys_test_and_set_bit' was not declared or defined.
sys_io.h:274: warning: documented symbol `static inline int sys_test_and_clear_bit' was not declared or defined.
Change-Id: Id10e9b6cd44a370ccc732c17b23fb66bd1845205
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
We will require 6 variables to be defined by SOC-specific
linker script; these values in turn can be pulled from
defines in layout.h.
To help position code correctly we define two new ELF sections
for this arch, 'reset' and 'exceptions'.
Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This header was pulled in verbatim from Altera HAL and had
some style and naming issues. The inline functions or macros
which read registers can now be used in expressions.
Change-Id: I7a463717051efd2f9dd36e8a84d357852fbf9215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In scenarios where device PM is enabled and dynamic irqs are
used, move the irq to vector table to RAM and keep it updated,
so that we can use this to restore IOAPIC/LOAPIC vector entries.
Jira: ZEP-224
Change-Id: I0d4350d4e30f8ca337a2a1d4f012748c3cb450f4
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
For EM Starter Kit, one of the SOC choices has DRAM and no FLASH.
If FLASH_SIZE is 0, the linker command file will create
SRAM, ICCM and DCCM memories (and no FLASH). SRAM is really DRAM.
Also, the linker.ld file is extended to handle microkernel
objects.
linker_harvard.ld has "all rights reserved". added to banner.
Change-Id: Ia433578b94ce91722f3670819f44befafeecf878
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
I've tested that CONFIG_XIP does work with Harvard.
User's can build CONFIG_XIP=y, and then have their bootable image
be placed in SPI-FLASH. A bootloader will load up ICCM contents.
Zephyr will then copy remaining data from ICCM to DCCM.
This takes a bit of ICCM memory to do it, but it will work.
Change-Id: Ic1cd201d19aab9083d63334527d9d68f4edc6075
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Some ARC CPUs can be built with separate instruction bus
and data bus (i.e. Harvard Architecture). Such systems
have only ICCM and DCCM memories. When CONFIG_HARVARD
is defined, the initial stack pointer is set to the
TOP of the DCCM memory. Currently there is no SOC that
existing in Zephyr tree that sets CONFIG_HARVARD, but
this will be coming soon.
Change-Id: I2016d1f472fbdad683a964aa0b65c5263ecfb6cf
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The stub label is created with ISR and IRQ number since the same
ISR can be used by several IRQs
Change-Id: I0ea909fddbce7a70c754befd095b7a3b36fffab4
Signed-off-by: Fabrice Olivero <fabrice.olivero@intel.com>
