STM32H7B3 supports max SYSCLK and AHB clock frequencies of 280 MHz,
and max APB frequency of 140 MHz
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
An optional reference to the temperature sensor can be obtained at
compile time, update implementation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit sets the power down bit of the module SDP, UART3, UART4,
and I3C by default. The module's driver should take the responsibility
to clear it to turn on the power. It helps reduce the power consumption
when an application doesn't use these modules.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This corrects the following:
1. The priority of type cast is lower than member access. So don't need
the redundant parentheses.
2. The macro should be added to the parentheses.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
1. Update to add support for Flexcomm8-13.
2. Fix the clock control driver, the enclosing #define
was incorrect.
3. Identify HS_SPI port using the appropriate Register
define
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Recent changes in this function made the code now compatible
with the use of LL API to perform this configuration.
Use it to simplify the driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Voltage scaling computation should be done in multiple cases.
Add a function that takes into account all cases.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.
Signed-off-by: Gennady Kovalev <gik@bigur.com>
Fixes#40730.
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In case of MSIS selected as system clock source it is necessary
to set Voltage scaling (VOS) when freqency is greater than 24MHz
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When MSI trimming values where set to 0,
and MSIS is used as system core clock and MSI > 4 MHz,
it causes uart to fail.
There is no need to set thoses trimming values.
So keep the default reset value. (keep ST Factory calibration)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Because on stm32u5 MSIS is the default clock after reset,
changing MSIS range means immediate frequency change.
Thus it is important to do it after flash latency change
in case of higher new frequency.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is fixing the error on clock control for the AHB3
in the stm32_clock_control_off function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
When CLOCK_CONTROL_NRF_FORCE_ALT is enabled then calibration is
performed outside of the driver. In that case certain Kconfig
options where present which were dedicated for case when calibration
is performed by the driver. Side effects of those options lead to
conflicts when CLOCK_CONTROL_NRF_FORCE_ALT was enabled. Fixed
those conflicts by introducing Kconfig option which indicates
whether calibration is performed by the driver or not.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
When existing stop mode 1&2, VCO is set to range 4
and should be set back to range 1 to allow full speed
operations.
Rather than setting VCO at startup, set it inside clock
setting procedure so that it could done
in clock reset procedure when existing stop modes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This constraint on the AHB prescaler is removed.
The ahb-prescaler is allow from 1-512.
For stm32 common and stm32U5 devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When the MSI clock is selected as source on the stm32wbx device,
the MSI has a range to choose the MSI input frequency.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On STM32WL, HSE clock can take 2 specific options:
-hse-tcxo
-hse-div2
Enable support for these options.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enable PWR clock unconditionally for L4, L5 and U5
like it is done on other stm32 series
Fixes#37781
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
