This commit relaxes the idle event statistics test precision requirement
for emulated QEMU targets because the cycle counts may be inaccurate when
the host CPU is overloaded (e.g. when running tests with twister) and a
high failure rate is observed for this test in the CI.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Test was previously relaxed for RISCV machine timer. I have a
platform where it fails on RISCV requiring further relaxation.
Relaxing precision for RISCV architecture.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit relaxes the precision requirements for idle event statistic
test when RISC-V machine timer driver is used. This is needed for some
platforms (e.g. hifive1), for which the cycle count is too low to pass
the checks where a percent deviation of peak cycles count is allowed.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
As the type of A(n) is integer, and A3 and A5 are close to
each other. Sometimes A3 is equal to A5. So change the ">" to
">="
Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>
