Make it possible to run in other posix boards.
By default, if the POSIX board does not define the TICK_IRQ
just run without that part of the test, printing a note.
The place where other POSIX boards should define it, is also
clear, and should be easy to keep those lines free from merge
conflicts in the future.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
On some devices, when k_cpu_idle() was called we were getting
interrupts that were not the timer interrupt. On bbc_micro
a power clock control driver interrupt was happening instead
and k_cpu_idle() was returning without the system tick advancing,
failing the test.
The clock control interrupts seem to only happen early in device
boot; moving the idle test much later lets the test pass on this
board (and likely all other NRF5 based boards).
Issue: ZEP-2257
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The hard-coded value of 10ms doesn't take the system configured
amount of ticks per second, nor does it account for an unlucky
tick advance which causes the test to fail very intermittently
in QEMU.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I6c676bc6c5e850a8725785554cd535e32067f33e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
tests/kernel/context:
added test point to cover k_cpu_atomic_idle.
Jira: ZEP-1242
Change-Id: Id09c89fd367d527ea1087e6eb2bdba29a338ceaf
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This option is added in order to support Xtensa, which needs more stack than
other architecture. This allows having a centralized way to change stack
requirements for all tests.
This extra stack size is eaqual to 0 for most architectures, except Xtensa
which requires additional 768 bytes for each stack.
Change-Id: Ie5dcae1dfd29018d36ef35dae22dc4c1a2ecdc14
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The for loop could exit with a out of bounds (variable j) value for
the delayed_threads array, we verify for the variable value before
operating on the array
This issue was reported by Coverity
Coverity-CID: 160078
Change-Id: I6aa1cc325cc363be48cd72b2a58d0a55ec3854bc
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I43a5c5112d694efdc14c5a0bcb4cafdc196d2680
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This is the port of the legacy/kernel/test_context test case to
the unified kernel
Change-Id: I344ac240eb3b48042477f8875115fdc3fca1154a
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
