zephyr

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Commit Graph

Author	SHA1	Message	Date
Filip Kokosinski	06615c148d	tests/kernel/usage/thread_runtime_stats: relax precision test for RISC-V This commit relaxes the precision requirements for idle event statistic test when RISC-V machine timer driver is used. This is needed for some platforms (e.g. hifive1), for which the cycle count is too low to pass the checks where a percent deviation of peak cycles count is allowed. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>	2022-06-13 13:21:16 -04:00
Hu Zhenyu	001cae0a5a	test: Increase the tolerance between A3/A5 As the type of A(n) is integer, and A3 and A5 are close to each other. Sometimes A3 is equal to A5. So change the ">" to ">=" Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>	2022-06-10 07:08:49 -04:00
Peter Mitsis	e83dde1628	tests: runtime threads stats Adds tests to verify the gathering of thread runtime stats. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>	2022-05-13 10:19:53 -05:00

Author

SHA1

Message

Date

Filip Kokosinski

06615c148d

tests/kernel/usage/thread_runtime_stats: relax precision test for RISC-V

This commit relaxes the precision requirements for idle event statistic
test when RISC-V machine timer driver is used. This is needed for some
platforms (e.g. hifive1), for which the cycle count is too low to pass
the checks where a percent deviation of peak cycles count is allowed.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

2022-06-13 13:21:16 -04:00

Hu Zhenyu

001cae0a5a

test: Increase the tolerance between A3/A5

As the type of A(n) is integer, and A3 and A5 are close to
each other. Sometimes A3 is equal to A5. So change the ">" to
">="

Signed-off-by: Hu Zhenyu <zhenyu.hu@intel.com>

2022-06-10 07:08:49 -04:00

Peter Mitsis

e83dde1628

tests: runtime threads stats

Adds tests to verify the gathering of thread runtime stats.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>

2022-05-13 10:19:53 -05:00

3 Commits