The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The implementation of GIC v3 ITS uses k_aligned_malloc(), which will
only work if dynamic memory is available (system heap). Tell the user
that a dynamic memory pool is required.
The amount of memory will depend on registers probed during runtime.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
We need to ensure that the XEC GIRQs are initialized after the
XEC ECIA device. Right now we depend on the linker ordering
things correctly since everything is at INTC_INIT_PRIORITY
priority
Set the XEC GIRQs to 41 so the init priority is one more than
INTC_INIT_PRIORITY that is used by xec-ecia.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Setting the same callback with the same data as is already configured
should not cause an error.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
remove all #ifdef CONFIG_SOC_SERIES_STM32xx
before to add a st,stm32g0-exti compatible
added to the matching targets:
C0/G0/U5/L5/MP1:
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Fix IDU mask setup:
* fix GENMASK usage to avoid generating mask to one extra cpu (which
doesn't exist in configuration)
* use arch_num_cpus() instead of CONFIG_MP_NUM_CPUS to allow having
some cpu's disabled (with detection in runtime)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Currently we setup irq trigger type (pulse or level) in IDU
before we Mask (disable) IRQ line.
The IDU is disabled at this moment, however we still may
accidentally generate interrupt by trigger setup.
To avoid that let's mask (disable) IRQ before trigger type setup.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This change takes advantage of line information coming from new properties
to simplify exti_irq_table definition and isr routing related code.
All __stm32_exti_isr_x routing functions are removed and instead,
stm32_exti_isr is now taking a exti_range structure which provides,
for each irq, start line and range length.
This argument is provided by IRQ_CONNECT macro instead of previous
dev info (which is constant and doesn't need to be provided as argument).
line_range_x variables are generated at driver init thanks to a
mix of dt magic and runtime implementation:
DT_FOREACH_PROP_ELEM iterates over each irq line (counted as
interrupt-names property) call a macro which instantiates populated
line_range_x variables, and calls IRQ_CONNECT for each IRQ.
Additionally, at each iteration stm32_fill_irq_table() is called to
fill exti_irq_table.
Since not required anymore, Kconfig symbols EXTI_STM32_EXTIX_Y_IRQ_PRI
are removed. IRQ prio is now supposed to be configured in device tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
zephyr kernel header file should be included otherwise gcc will report
the warning: implicit declaration of function 'k_aligned_alloc' and
the return value of 'k_aligned_alloc' will be treated as an int type,
which will cause an error on the 64 bits platform.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.
Enable nocache in each driver use it.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Control shared interrupts enabling/disabling via IDU.
With that we can easily enable and disable them for all cores
in one place.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.
This driver is required to manage GPIO interrupts.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
GICR_TYPER is a 64 bit register. On AArch32 when one uses sys_read64(),
this results in ldrd instruction. When Zephyr runs as a VM, 'LDRD'
instruction on an emulated MMIO region gets trapped to the hypervisor as
data abort.
Refer the following paragraph from ARM DDI 0487G.b ID072021 :-
Section - "ISS encoding for an exception from a Data Abort",
"For other faults reported in ESR_EL2, ISV is 0 except for the following
stage 2 aborts:
AArch32 instructions where the instruction:
— Is an LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, LDRSB, LDRSBT,
LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, STRB, STLB, or STRBT
instruction."
As 'LDRD' is not in the list, so ISV==0. This implies that Arm could not
decode the instruction for the hypervisor (in EL2) to execute it.
Thus, we have abstracted this read into arm_gic_get_typer().
For AArch64, we use sys_read64() as before.
For AArch32, we use sys_read32() twice to read the lower and upper 32 bits
of GICR_TYPER.
Thus, we ensure that when the access is trapped for AArch32, Arm generates
a valid ISS so that hypervisor can execute it.
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Replace usage of CONFIG_MP_NUM_CPUS with CONFIG_MP_MAX_NUM_CPUS for
init and declaration as we phase out CONFIG_MP_NUM_CPUS usage.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix the scope of some variables in various STM32 drivers including:
- SDMMC
- DMA
- OSPI/QSPI Flash
- Interrupt controller
The variables are set static instead of global and const if appropriate.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some files were using arch interfaces (e.g. arch_curr_cpu) without
including necessary headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the incoming removal of kernel.h/types.h from init.h, lots of files
start to show compile errors because they relied on indirect
definitions, including errno.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Zephyr encodes multi-level interrupts in a certain way, and
the driver is not utilizing the encoding correctly. So fix
it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduce a function to do the matching job. Add the config for some
platforms to match the mpdir with aff0 only.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Some platforms only use aff0 to match mpdir and GICR.aff. Introduce
GIC_V3_RDIST_MATCHING_AFF0_ONLY to set the matching method only using
aff0. With this config enabled, the matching function will find the
target redistributor by comparing the aff0 only.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The cast for the offset variable will make incorrect register
access when it is over 0x80. Change the char cast to unsigned
char to fix it.
Fixes#49803.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
In old way, gic_rdists[cpu] is calculated via MPIDR_TO_CORE(), but in
real hardware, MPIDR_TO_CORE() isn't a value increment from 0 one by
one, and that will lead gic_rdists[cpu] to point to a wrong address.
GICv3 provides the register GICR_TYPER[1] and it has a field named
Affinity_Value. This field can help to determine where gic_rdists[cpu]
should point.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Updates ESP32 to use hal interrupt funcions provided by 4.4.1
release. Removed redefinition of interrupt FLAGS.
This also includes interrupt definitions for ESP32C3
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
