Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.
States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled
Jira: ZEP-994
Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.
x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.
Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ARC does not align data structures by 4 bytes by default.
Add necessary linker sections.
Change-Id: I3bf7aa38b9bc8cba56f824469040c027968fa564
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
ARC interrupts can be either level or pulse.
Level interrupts remain asserted until the interrupt service routine
clears the interrupt at the peripheral. This is the default and most
common case.
Pulse interrupts have an extra flip-flop that converts a pulse to a
level. The ARC auto-clears this level as the interrupt service routine
is entered. As such, an interrupt handler for a pulse interrupt need
not clear the interrupt.
It is the rare device that uses pulse interrupts.
Nothing currently calls this inline function so ARC interrupts are
LEVEL by default.
(see ZEP-83)
Change-Id: I09ef86aae1926c1327e82ff99c2f8aa7eabde684
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Binutils ld has an annoying misfeature (apparently a regression from a
few years ago) that alignment directives (and alignment specifiers on
symbols) apply only to the runtime addresses and not, apparently, to
the load address region specified with the "AT>" syntax. The net
result is that by default the LMA output ends up too small for the
addresses generated in RAM. See here for some details:
https://sourceware.org/ml/binutils/2013-06/msg00246.htmlhttps://sourceware.org/ml/binutils/2014-01/msg00350.html
The required workaround/fix is that AFAICT any section which can have
inherit a separate VMA vs. LMA from a previous section must specify an
"ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of
sync and the XIP data will be wrong at runtime.
No, I don't know why this isn't the default behavior.
A further complexity is that this feature only works as advertised
when the section is declared with the "AT> region" syntax after the
block and not "AT(address)" in the header. If you use the header
syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply
padding and the LMA ends up to big. This is almost certainly a
binutils bug, but it's trivial to work around (and the working syntax
is actually cleaner) so we adjust the usage here.
Note finally that this patch includes an effective reversion of commit
d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which
was an earlier workaround for what seems to be the same issue.
Jira: ZEP-955
Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Arduino 101 comes with a bootloader that supports DFU
and flashing of all cores using the dfu-util package.
This changes the memory layout of the image built for the
Arduino 101 and remove previous work-arounds to allow booting,
including the version-header section in the linker script.
The bootloader expects the text section at +0x30 from the physical
load address and thus requires special treatment in the linker
script.
Other changes by Andrew Boie:
The flash size parameters were both wrong. X86 side has 192K
of flash from 0x4003000 - 0x40060000, the entire span of
sys_flash1.
ARC side is now the span from 0x40010000 - 0x40030000, 128K.
Change-Id: Iecfa5d2b84a3f522d9eca06268d6b8b71a094aaa
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In 1.0 you could set only one callback on the whole gpio controller. It
was impossible for another sub-system to add another callback, without
overwritting an existing one.
Such API has been obsolete for a long time and no one is using it
anymore. Thus removing it entirely.
Change-Id: I6a17fd99373dc6cef1fa2ebb421e992412d5015e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Commit 3e63a74514 did not revert properly
things.
Change-Id: I792d5698966542ce2cfb9f858c56b30c392f02a2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
These files were almost exactly the same and had already started
bit-rotting (note the missing net_l2 section in linker_harvard.ld)
Issue: ZEP-528
Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Follow up to TSC decission for further discussion in the networking
WIG.
Change-Id: I148b484dfe308661573e47ed3e60cceed673bddf
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Net core then does not know anything about l2 related logic.
For instance ARP is used in ethernet l2 API and nowhere else.
This will be helpful when adding different technologies altogether.
Currently, only SLIP driver is enabled to use relevant l2 layer.
Change-Id: I03c93326321028d04222733ca4083e3c6b785202
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will be used by the new network stack to relate a device to actual
network context, and used in the different layers (mac, ip ...).
Change-Id: I30c08fa975314544c36b71636fd9653d562891b3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The problem is doxygen's parser is getting confused by constructs as:
static inline __attribute__((always_inline))
void sys_out8(uint8_t data, io_port_t port)
{
_arc_v2_aux_reg_write(port, data);
}
Too many words at the beginning of the function definition. So change
to use the macro ALWAYS_INLINE (which is already defined to mean
'inline __attribute__((always_inline))`.
Kills:
sys_io.h:37: warning: documented symbol `static inline void sys_out8' was not declared or defined.
sys_io.h:47: warning: documented symbol `static inline uint8_t sys_in8' was not declared or defined.
sys_io.h:58: warning: documented symbol `static inline void sys_out16' was not declared or defined.
sys_io.h:68: warning: documented symbol `static inline uint16_t sys_in16' was not declared or defined.
sys_io.h:79: warning: documented symbol `static inline void sys_out32' was not declared or defined.
sys_io.h:89: warning: documented symbol `static inline uint32_t sys_in32' was not declared or defined.
sys_io.h:120: warning: documented symbol `static inline int sys_io_test_bit' was not declared or defined.
sys_io.h:133: warning: documented symbol `static inline int sys_io_test_and_set_bit' was not declared or defined.
sys_io.h:146: warning: documented symbol `static inline int sys_io_test_and_clear_bit' was not declared or defined.
sys_io.h:161: warning: documented symbol `static inline void sys_write8' was not declared or defined.
sys_io.h:171: warning: documented symbol `static inline uint8_t sys_read8' was not declared or defined.
sys_io.h:182: warning: documented symbol `static inline void sys_write16' was not declared or defined.
sys_io.h:192: warning: documented symbol `static inline uint16_t sys_read16' was not declared or defined.
sys_io.h:248: warning: documented symbol `static inline int sys_test_bit' was not declared or defined.
sys_io.h:261: warning: documented symbol `static inline int sys_test_and_set_bit' was not declared or defined.
sys_io.h:274: warning: documented symbol `static inline int sys_test_and_clear_bit' was not declared or defined.
Change-Id: Id10e9b6cd44a370ccc732c17b23fb66bd1845205
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
For EM Starter Kit, one of the SOC choices has DRAM and no FLASH.
If FLASH_SIZE is 0, the linker command file will create
SRAM, ICCM and DCCM memories (and no FLASH). SRAM is really DRAM.
Also, the linker.ld file is extended to handle microkernel
objects.
linker_harvard.ld has "all rights reserved". added to banner.
Change-Id: Ia433578b94ce91722f3670819f44befafeecf878
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
I've tested that CONFIG_XIP does work with Harvard.
User's can build CONFIG_XIP=y, and then have their bootable image
be placed in SPI-FLASH. A bootloader will load up ICCM contents.
Zephyr will then copy remaining data from ICCM to DCCM.
This takes a bit of ICCM memory to do it, but it will work.
Change-Id: Ic1cd201d19aab9083d63334527d9d68f4edc6075
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Some ARC CPUs can be built with separate instruction bus
and data bus (i.e. Harvard Architecture). Such systems
have only ICCM and DCCM memories. When CONFIG_HARVARD
is defined, the initial stack pointer is set to the
TOP of the DCCM memory. Currently there is no SOC that
existing in Zephyr tree that sets CONFIG_HARVARD, but
this will be coming soon.
Change-Id: I2016d1f472fbdad683a964aa0b65c5263ecfb6cf
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The ARC CPUs have several other features controlled by aux registers.
Specifically, I will be needing ones for i-cache, d-cache and various
BUILD registers that indicate which features are present.
Change-Id: If15a330f4ea5aa519655f88526fbb5f600d7cc0b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Indentation should be with tabs only (these lines were with tab +
spaces).
Change-Id: I8f199b1d6972b02513e4c293636606f481641266
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
To boot zephyr on the Arduino 101 running the original bootloader
which supports DFU, set the following in your application configuration
file:
CONFIG_SS_RESET_VECTOR=0x40034000
CONFIG_PHYS_LOAD_ADDR=0x40010000
CONFIG_VERSION_HEADER=y
Jira: ZEP-219
Change-Id: Ia015a7b6fce888b49ed22c558de992132d4713ea
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove hardcoding and make the values configurable. Also make the
Kconfig variables consistent with other architectures.
Change-Id: I69334002303d4d8abaf7363d9134fd5f46ce4eeb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Many sub-systems might require to set a callback on different pins.
Thus enabling it via changing the API.
It is also possible to retrieve private-data in the callback handler
using CONTAINER_OF() macro (include/misc/util.h).
Former API is still available, and is emulated through the new one.
Using both should not be a problem as it's using new API calls.
However, it's now better to start using the new API.
Change-Id: Id16594202905976cc524775d1cd3592b54a84514
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
ARC CPU has stack checking feature that allows to trigger an exception
whenever the stack is incorrectly accessed.
This patch implements the stack_top and stack_base register updates on
context switches, and activates the Stack Checking bit of STATUS32
register when the CPU is in the context of a fiber or task.
As GCC accesses the non-yet allocated stack with frame pointer enabled,
this patch also add the omit-frame-pointer gcc flag in order to work
properly.
Change-Id: Ia9e224085a03bd29d682fb8f51f8e712f2ccb556
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
Use of these is the mark of a deranged imagination.
Change-Id: Ib4b5f78cf61c016e333288090b397e9a3e0b8a40
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are guaranteed to work for bitfields that are
larger then 32 bits wide.
Change-Id: I39a641f08a255478fae583947bced762950d12ff
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Adds static irq support for the Quark SE platform for the ARC core.
New linker sections and sw isr table initialization is needed to support
static IRQ.
Change-Id: I82af98a189f5a156e7f1018f3ecdbfa73ad3e6ef
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Adds support for static IRQ handler initialization.
Currently, IRQ_CONNECT and IRQ_CONFIG macros are emulating static
behavior through dynamic initialization.
This commit updates the macros to get real static initialization.
IRQ handlers must be assigned at build time.
Change-Id: Ia07fb25a5e4dae489f84ffcedb28007ee18a3b82
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
IRQ_CONNECT_STATIC takes 6 arguments on other
architectures, but the ARC one had only 5.
Change-Id: I257e8db12582ee2d6f93bba63af9aa597197a53d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Uses the "trap_s" exception to simulate entry into IRQ context;
offloaded functions run on the FIRQ stack.
Change-Id: I310ce42b45aca5dabd1d27e486645d23fa0b118f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This way, it does not fall in the middle of a group, like the RAM group
and as a side-effect potentially move the dot (current address pointer).
Change-Id: Iefbff8bbeadfc740dee61154d7db99b7b7aad6d6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The linker scripts for the quark_se_ss and generic_arc platforms are the
exact same, so extract the contents in an includable file.
Change-Id: I2cb90a6f819b12db77880228e41ff14c9755d59a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
These should now work for drivers written for other arches.
Still a hack to do all the IRQ setup at runtime.
Change-Id: I9717f74abef3b9934f9a1c0acbd76d960ed7a3cb
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
This commit adds asm implementation for the methods:
sys_io_set_bit
sys_io_clear_bit
sys_io_test_bit
sys_io_test_and_set_bit
sys_io_test_and_clear_bit
Change-Id: I144568e113316fa43d943cdc5457cb17e66839c3
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
