This board seems to have issue with data alignemnt after 843f66f and is
failing in CI. Exclude it while the problem is investigated.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Let's make this official: we use the suffix `_MASK` for the define
carrying the GENMASK for the attributes, and the suffix `_GET(x)` for
the actual macro extracting the attributes.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The test_sem_take_timeout_isr depends on the thread's priority. But for
SMP platforms, the priority is different with no-SMP. High-priority
threads and low-priority threads might run simultaneously at different
cores. Set the test case run at 1cpu to fix such an issue.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The heap size is not enough so that it will cause the testcase fail.
Increase to 32k to make sure it works for a long time in the future.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The test assumed that interrupt line 5 was up for grabs, but it
is not in general. (For ex., on an nrf53_bsim this is the clock
interrupt, which cannot be hijacked).
Instead, for boards that define it, let's use the int line
used for offloading SW interrupts (which is defined for all posix
arch boards in tree)
And if this is not defined, let's skip the test.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The mr_canhubk3 board enables by default an off-chip watchdog that must
be serviced to avoid triggering a reset and cannot be disabled on a
per-test basis.
test_all_stats_usage assumes the CPU was never idle before the test
starts but this is not the case for mr_canhubk3 because the off-chip
watchdog driver has a thread kicked off during device init that will
conflict with the expected usage stats on this test. So skip this test
for this board.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The _EXPIRED macro is no longer necessary. It is a relic of an older
timeout processing algorithm from several years ago.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Zephyr device and device.pm tests uses device tree fragments applied
to main board device trees. For xenvm they have conflicting
address/size cells definition with board DT. It leads to CI and test
issues during build (xenvm has 0x2 cells, tests have 0x1).
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
In test_kobject_perm_error, there are 13 kobjects to test but
the loop only do 12. So amend the code to test all 13 kobjects.
Also remove the parameter of tid to child thread as the child
thread is not using it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This header does not expose any public APIs, so move it under
kernel/include and change files including it.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently spinlock internals are directly accessed from the tests.
This way the test becomes bound to the particular spinlock implementation.
To remove this unnecessary dependency the distinct API to check if spinlock
is locked is introduced.
k_spin_is_locked should be used for the spinlock testing only,
so the scope of this API is intentionally restricted.
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
With picolibc being the default C library, we need to explicitly include
testing against the minimal C library for kernel components.
Signed-off-by: Keith Packard <keithp@keithp.com>
Modify the signature of the k_mem_slab_free() function with a new one,
replacing the old void **mem with void *mem as a parameter.
The following function:
void k_mem_slab_free(struct k_mem_slab *slab, void **mem);
has the wrong signature. mem is only used as a regular pointer, so there
is no need to use a double-pointer. The correct signature should be:
void k_mem_slab_free(struct k_mem_slab *slab, void *mem);
The issue with the current signature, although functional, is that it is
extremely confusing. I myself, a veteran Zephyr developer, was confused
by this parameter when looking at it recently.
All in-tree uses of the function have been adapted.
Fixes#61888.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Fix few mismatched CONTAINER_OF, going from struct k_work to struct
triggered_test_item should pass by struct k_work_poll.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix few instances of delayable work handlers using the k_work pointer
directly in a CONTAINER_OF pointing to a k_work_delayable.
This is harmless since the k_work is the first element in
k_work_delayable, but using k_work_delayable_from_work is the right way
of handling it.
Change a couple of explicit CONTAINER_OF doing the same work as the
macro in the process.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
CONFIG_COVERAGE has been incorrectly used to
change other kconfig options (stack sizes, etc)
code defaults, as well as some samples behaviour,
which should not have dependend on it.
Instead those should have depended on COVERAGE_GCOV,
which, being the one which adds special code and
temporary RAM storage for embedded targets,
require changes to many features.
When building for the native targets, all this was
unnecessary.
=> Fix the dependency.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This test fails when icount is disabled, so enable it
See 7bdc621ba9 which disabled icount by
default for this platform.
Signed-off-by: Keith Packard <keithp@keithp.com>
Some 64 bit platforms do not have MMU, however the 64 bit platfoms need
a larger stack. This testcase fails with non-MMU 64 bit platform e.g.
v8r64 platform due to the stack overflow. To fix this issue, set 2k
stack for all 64 bit platforms (CONFIG_64BIT) as this is likely a common
issue for all non-MMU 64 bit platforms.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The heap size is set to 20000 which is just not enough for v8r platform.
Fix testcases failure in tests/kernel/threads/ by increasing the heap
size to 21504.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This follows the same convention that has already been adopted by Intel
Alder Lake and Raptor Lake boards.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The original issue is fixed some time ago, so re-enable the
test.
This reverts commit 52992b0658
("tests: skip the cpu_idle test for nsim_hs_smp")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Some architectures such as RISC-v support more than 255 interrupts
per aggrigator. This diff adds the ability to forgo the aggrigator
pattern and use a configurable number of bits for multilevel
interruts.
Signed-off-by: Joshua Lilly <jgl@meta.com>
Adding a new simple test that checks that canaries values
are different between threads when CONFIG_STACK_CANARIES_TLS
is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Introduce new API to compare two timepoint values to
find the one that is going to expire sooner, or is already
expired.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
The test_trylock reuses the cpu1_thread, but there is no way for it to
exit. This will cause the thread created twice, as a result, two cpu
running the same thread simultaneously cause an unexpected crash.
Fix this by adding initialization of resources and also the exit for the
cpu1_thread.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
With SMP, the private_mutex may not be locked fast enough by
thread_12 after the thread creation as it might take longer
for a thread to start running the entry function, resulting
in test failure when the main test thread goes into locking
it again. So give it a bit more delay after thread creation
so thread_12 has a chance to lock the private_mutex.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If CONFIG_SMP_TEST_RUN_FACTOR is zero, the switch torture test
is effectively not doing anything as the k_sleep() below is not
going to sleep at all, and all created threads are being
terminated (almost) immediately after creation. So if run
factor is zero, mark the test as skipped.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Commit a1d21ca69b ("tests: timer_behavior: don't fail the test with
timer wrap-arounds") simply ignored the total time validation whenever
any rollover was detected. Let's adjust the end timestamp according
to the number of rollovers instead.
Documentation for sys_clock_cycle_get_32() says it should count up
monotonically through the full 32 bit space, wrapping at 0xffffffff.
Therefore we just need to add 2^32 times the number of rollovers to
the end timestamp.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add support for dynamic thread stack objects. A new container
for this kernel object was added to avoid its alignment constraint
to all dynamic objects.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
