Commit Graph

4 Commits

Author SHA1 Message Date
Andy Ross
d1200d2155 tests: Never disable SMP
Disabling SMP mode for certain tests was a one-release thing, done to
avoid having to triage every test independently (MANY are not
SMP-safe), and with the knowledge that it was probably hiding bugs in
the kernel.

Turn it on pervasively.  Tests are treated with a combination of
flagging specific cases as "1cpu" where we have short-running tests
that can be independently run in an otherwise SMP environment, and via
setting CONFIG_MP_NUM_CPUS=1 where that's not possible (which still
runs the full SMP kernel config, but with only one CPU available).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-09-26 16:54:06 -04:00
Andy Ross
fc3ca95ba7 tests: Mass SMP disablement on non-SMP-safe tests
(Chunk 2 of 3 - this patch was split across pull requests to address
CI build time limitations)

Zephyr has always been a uniprocessor system, and its kernel tests are
rife with assumptions and outright dependence on single-CPU operation
(for example: "low priority threads will never run until this high
priority thread blocks" -- not true if there's another processor to
run it!)

About 1/3 of our tests fail right now on x86_64 when dual processor
operation is made default.  Most of those can probably be recovered on
a case-by-case basis with simple changes (and a few of them might
represent real bugs in SMP!), but for now let's make sure the full
test suite passes by turning the second CPU off.  There's still plenty
of SMP coverage in the remaining cases.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-02-28 12:47:12 -08:00
Spoorthi K
d155e88624 tests: stack_random: Add Ztest support
Add Ztest support for stack randomization test case.Ztest support for
stack randomization test case.

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
2018-04-05 08:07:43 -04:00
Andrew Boie
83752c1cfe kernel: introduce initial stack randomization
This is a component of address space layout randomization that we can
implement even though we have a physical address space.

Support for upward-growing stacks omitted for now, it's not done
currently on any of our current or planned architectures.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-16 16:25:22 -07:00