Commit Graph

21 Commits

Author SHA1 Message Date
Markus Fuchs
29630cc7fc samples: crypto: Add AES-GCM sample
Add sample for AES Galois/Counter Mode (GCM) of operation with a MACsec
GCM-AES test vector.
Also improve existing code by declaring expected ciphertext arrays as
constant.

Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
2020-02-08 13:40:33 +02:00
Markus Fuchs
20960911ca samples: drivers: crypto: Add STM32 driver support
Add STM32 CRYP driver support and a corresponding build-only test to
the crypto sample project.

Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
2020-02-07 10:45:51 -06:00
Andrew Boie
777213c0fb samples: drivers: crypto: fix test failure
The regular expressions used by this test to determine
success or failure get confounded if the log subsystem
drops the wrong messages due to buffers being full.

Just use minimal logging which synchronously logs
everything.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-01-13 16:35:10 -05:00
Anas Nashif
70758c4374 tests: fix test identifiers
The seasonal overhaul of test identifiers aligning the terms being used
and creating a structure. This is hopefully the last time we do this,
plan is to document the identifiers and enforce syntax.

The end-goal is to be able to generate a testsuite description from the
existing tests and sync it frequently with the testsuite in Testrail.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-12-09 15:53:44 -05:00
Daniel Leung
b7eb04b300 x86: consolidate x86_64 architecture, SoC and boards
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.

() Removes the x86_64:x32 architecture and SoC, and replaces
   them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
   qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-10-25 17:57:55 -04:00
Anas Nashif
6e6f13c18a samples: fix identifiers for samples
Fix identifiers for tests in samples.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-01 12:23:09 -04:00
Andy Ross
b69d0da82d arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().

The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.

Limitations:

+ Right now the SDK lacks an x86_64 toolchain.  The build will fall
  back to a host toolchain if it finds no cross compiler defined,
  which is tested to work on gcc 8.2.1 right now.

+ No x87/SSE/AVX usage is allowed.  This is a stronger limitation than
  other architectures where the instructions work from one thread even
  if the context switch code doesn't support it.  We are passing
  -no-sse to prevent gcc from automatically generating SSE
  instructions for non-floating-point purposes, which has the side
  effect of changing the ABI.  Future work to handle the FPU registers
  will need to be combined with an "application" ABI distinct from the
  kernel one (or just to require USERSPACE).

+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
  of all memory.  No MMU/USERSPACE support yet.

+ We are building with -mno-red-zone for stack size reasons, but this
  is a valuable optimization.  Enabling it requires automatic stack
  switching, which requires a TSS, which means it has to happen after
  MMU support.

+ The OS runs in 64 bit mode, but for compatibility reasons is
  compiled to the 32 bit "X32" ABI.  So while the full 64 bit
  registers and instruction set are available, C pointers are 32 bits
  long and Zephyr is constrained to run in the bottom 4G of memory.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-01-11 15:18:52 -05:00
Anas Nashif
733a054ab0 samples: fix sample tags
Use correct tags instead of obvious 'sample' tag.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-16 09:17:51 -04:00
Anas Nashif
c4d1324ce4 samples: crypto: move to new logger
Move sample to use new logger.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 17:49:12 -04:00
Flavio Ceolin
f6210cf430 samples: drivers: crypto: Fix minimum values for mbedTLS
The latest mbedTLS (2.12) release increased resources requirements on
Zephyr, so it was required increasing the minimum SRAM to run this test
and the main stack size.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-06 21:11:31 -04:00
Anas Nashif
d05442ee9c samples: crypto: adapt harness
Adapt console harness to new changes in sample output.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-06-05 10:26:59 -04:00
Leandro Pereira
d06eecbe29 samples: drivers: crypto: Update expected sample output
Some changes were made in the sample implementation that made the test
fail due to differences in the expected output.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-06-05 10:26:59 -04:00
Diego Sueiro
140daa2f27 sanitycheck: add min_flash option for 32K devices
Following tests were failing on a microcontroller with 32KB flash:
    test-mbedtls
    kernel.common

The min_flash option has been added in the test case yaml files.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-04-21 06:57:38 -07:00
Anas Nashif
5d3a534807 samples: use console harness for some samples
The output of those samples can be parsed and verified by sanitycheck,
so lets use the console harness for this.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-25 04:45:35 +05:30
Anas Nashif
c3880c0db4 samples: crypto: increase min_ram for sample
This samples does not fit on platforms with 8k RAM, increase minimal
requirements.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-13 10:48:36 -05:00
Anas Nashif
26ccc0bbcb samples: crypto: remove build_only and sample cleanup
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-28 20:24:29 -05:00
Anas Nashif
23f81eeb42 tests/samples: fixed yaml syntax
Use a map directory, avoid the list which makes parsing a bit
cumbersome.

Fixes #5109

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-11 14:47:08 -05:00
Anas Nashif
d55884a34d sample: crypto: also test mbedTLS config
expand testing to mbedTLS

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-16 05:48:16 -05:00
Anas Nashif
0356590df5 tests: samples: fix yaml syntax
Fix indentation and syntax and make it pass yamllint tool.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-15 08:15:00 -04:00
Anas Nashif
3c50f7aa12 tests: samples: remove duplicate filtering
We have many testcases doing filtering both on the architecture level
and the platform level, which is redundant. Also many testcases are
running the same test twice on the same SoC for no good reason, cleanup
the tests and cleanup the filtering.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-27 17:44:23 -04:00
Anas Nashif
cc24f4b03c tests: samples: convert testcase files to yaml
This will prepare test cases and samples with metadata and information
that will be consumed by the sanitycheck script which will be changed to
parse YAML files instead of ini.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-21 20:56:53 -04:00