This commit fixes the incorrect memory (FLASH and SRAM) size
specification in the device tree and the board test yaml files.
The `qemu_cortex_r5` board (using `fdt-single_arch-zcu102-arm.dtb` FDT)
has 64MiB RAM at the address 0 and 32MiB QSPI flash at 0xc0000000.
QEMU `info mtree`:
0000000000000000-ffffffffffffffff (prio 0, i/o): memory@00000000
0000000000000000-000000000002ffff (prio 0, ram): ddr_bank1_1@0x0
0000000000030000-000000000003ffff (prio 0, ram): ddr_bank1_2@0x30000
0000000000040000-0000000003ffffff (prio 0, ram): ddr_bank1_3@0x40000
00000000c0000000-00000000c1ffffff (prio 0, i/o): lqspi
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now
set zephyr,entropy in the chosen node of the device tree to the entropy
device.
This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also
remove any other stale ENTROPY related defines in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Don't assume in the soc level device trees that flexcomm nodes will
always be configured as spi. Instead, configure flexcomm nodes at the
board level for lpcxpresso55s69 and lpcxpresso54114 boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Don't assume in the soc level device trees that flexcomm nodes will
always be configured as usart. Instead, configure flexcomm nodes at the
board level for lpcxpresso55s69 and lpcxpresso54114 boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Don't assume in the soc level device trees that flexcomm nodes will
always be configured as i2c. Instead, configure flexcomm nodes at the
board level for lpcxpresso55s69 and lpcxpresso54114 boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The st,stm32l0-flash-controller did not have a binding, add one for it.
Also made a comment in stm32l0.dtsi that the driver doesn't currently
support this controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The flash at 0 is a cfi-flash and its 2 banks each that are 64M.
Update qemu-virt-a53.dtsi to reflect the proper flash config, however we
comment out the second bank of flash for now because zephyr,flash can
only handle one value in the reg property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Group all the GPIO controllers under a pinctl node so that we have a
container for pinmux configuration data.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds i2c device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new i2c driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Make sure every flash controller has a node label "flash_controller".
This will make it easier to refer to the SoC NVMC node when necessary.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Define rng nodes for all SoCs featuring the RNG peripheral,
so that the entropy_nrf5 driver can be converted to DTS.
For the network core in nRF5340, align the RNG interrupt priority with
what is used as the default value in (almost) all other DTS nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Currently supported nRF SoCs featuring the second GPIO port (P1) do not
have all 32 pins implemented in that port. Add the "ngpios" property
in gpio1 nodes for these SoCs, so that they don't take the default
value of 32 to indicate the number of available pins but use instead:
- 10 for nRF52833
- 16 for nRF52840
- 16 for nRF5340 (both application and network core)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the STM32L422Xb SoC. Base stm32l422.dtsi on
stm32l412.dtsi to be able to add the crypto device later.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
64 kB of memory is reserved for the inter-processor
communication. this makes sense only if RPMsg is used.
Allow to use this memory for firmware data by default.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
This commit adds a GMAC instance to the SAM V71 device tree, with the
chip revision-specific hardware queue count.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds a GMAC instance to the SAM E70 device tree, with the
chip revision-specific hardware queue count.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
SIM core system clock is being used, but more importantly this will
enable to get the SIM clock controller in use for power management
purposes in MCUX ethernet driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.
Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.
Signed-off-by: Kieran Levin <ktl@frame.work>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert the driver to use DT_INST_ defines, update all dependent dts,
soc and board files.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The `xlnx,ttcps` binding, despite having the file name of
`xlnx,ttcps.yaml`, had the compatible property of `cdns,ttc`.
While it is true that the Xilinx ZynqMP platform embeds the Cadence
Triple Timer Counter (TTC) IP core, its TTC differs from the original
Cadence core in that it implements 32-bit counters, instead of the
16-bit counters defined in the original; hence, the Xilinx variant is
not compatible with the original Cadence version and should be treated
as a different device.
This commit changes the `xlnx,ttcps.yaml` compatible property to
`xlnx,ttcps` for the above reasons.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add a fixed clock to the qemu-virt-a53.dtsi to match how the musca dts
files work so we get the clock DT info in the same way in the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add entropy driver based on GECKO TRNG module along with device
tree support for EFM32PG and EFR32MG SOCs.
Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
Convert usb_stm32 driver to use of DT_INST macros.
Since driver is compatible with 3 different dt compatibles and
compatible string is included in DT_INST macros, I've kept the
DT_USB_ compatible agnostic macros based on DT_INST ones, which
allowed to remove fixup definitions.
Use of DT_USB symbols is now limited to usb_dc_stm32.
Additionally, compatible "st,stm32-otgfs" is removed from list
of compatibles for usbotg_hs ips.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.
Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.
Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"
This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a property to the nxp,kinetis-gpio binding that related the GPIO
node to the pinmux PORT node.
For the kl25z we add the pinmux nodes as well since they didn't exist.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enable counter driver support for H7 series. Tested with H743ZI MCU
using samples/drivers/counter/alarm.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
