The TOOLCHAIN_DISABLE_WARNING/TOOLCHAIN_ENABLE_WARNING macros are easier
to read and compiler agnostic.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Add some overlay files for the silabs xg29_rb4412a board to enable tests
on the board. Also add the platform to some testcase.yaml files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The number of mpu regions that can be configured is less than four cases.
Therefore, only remove this case on cm33 cores, failed log show below:
"num_parts of 4 exceeds maximum allowable partitions (3)"
samples: kernel: mem_protect: userspace: remove mimxrt700_evk cm33 cores
The maximum number of partitions is less than the number of partitions
currently required, causing case to be unable to apply for or delete
excess regions.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This adds data cache manipulations, flushing and invalidation,
to the tests where buffer content are being written and
compared. These tests map different virtual pages to the same
physical pages, and write to one of the mapped virtual
addresses. Some SoCs may cache the virtual address separately
and writes to one virtual address will not be reflected to
another virtual address, this failing the comparison. So we
need to manually flush the cache after writing to the buffer,
and invalidating cache before reading. Note that not all reads
and writes need this treatment as some of them only needs to
test for access permissions, and not the memory content.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For CPUs with incoherent cache under SMP, the tests to read/write
buffer (... majority of tests here) may not work correctly if
the test thread jumps between CPUs. So use the test infrastructure
to limit the test to 1 CPU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both tests set CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=0 so extract
it to prj.conf. The tests require malloc arena size to be 0 to
run successful. By refactoring the config, it is now able to
with west build and still passing.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Amend the filtering so that the normal mem_map (with exec) test
is not going to run on Intel Audio DSP SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With the rename of intel_adsp/ace30_ptl to intel_adsp/ace30/ptl,
the "sim" variant no longer inherit the base configuration. So
make a copy of the .conf file to explicitly target the sim
variant.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Obviously, everyone knows that there are 8 bits per byte, so
there isn't a lot of magic happening, per se, but it's also
helpful to clearly denote where the magic number 8 is referring
to the number of bits in a byte.
Occasionally, 8 will refer to a field size or offset in a
structure, MMR, or word. Occasionally, the number 8 will refer
to the number of bytes in a 64-bit value (which should probably
be replaced with `sizeof(uint64_t)`).
For converting bits to bytes, or vice-versa, let's use
`BITS_PER_BYTE` for clarity (or other appropriate `BITS_PER_*`
macros).
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
What is changed?
- Added a new mps3 board an552 for the soc corstone300.
The qualifier to build/run application with board mps3/an552 is
`mps3/corstone300/an552` for secure and
`mps3/corstone300/an552/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone300
and it uses the ARM FVP `FVP_Corstone_SSE-300_Ethos-U55`.
The qualifier to build/run application with FVP is
`mps3/corstone300/fvp` for secure and
`mps3/corstone300/fvp/ns` for non-secure.
- Note: the qualifier to build/run application with board mps3/an547
is now changed to
`mps3/corstone300/an547` for secure and
`mps3/corstone300/an547/ns` for non-secure.
How is it changed?
- Moved common code from mps3/an547 to corstone300.
- Renamed soc for an547 to corstone300 and added
a new soc corstone300/an552.
Why do we need this change?
- This enables FVP support and testing for corstone300.
- SOC/qualifier for mps3/an547 was renamed to reduce code redundancy
- A separate FVP variant was added for AN552 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone300/fvp` should be used when testing
AN552 with FVP and `arm/mps3/corstone300/an552` should be used when
testing with AN552 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The test_k_mem_map_unmap test requires some free physical pages
to work correctly. On qemu_x86_tiny, the physical memory is
artificially limited to test demand paging, which is 320KB as
of writing of this commit message. We also reserve 128KB of
physical memory as swapping area. And we do pin quite lot of
text and data (relatively speaking) in memory. There is not
much memory left for the test. So lower the amount of reserved
memory for paging to leave some pages for the test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This needs special treatment because the TEST_MEM_MAP section
is placed at the end. Since there is code in TEST_MEM_MAP,
rimage thinks the whole text section spans from .text to
end of TEST_MEM_MAP, which overlaps .data and others, so
it complains. Skip the execution test to avoid this issue.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The board has been renamed from intel_adsp/ace30_ptl to
intel_adsp/ace30/ptl. So the corresponding board only configs
for tests also need to renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
Up until now, the `__thread` keyword has been used for declaring
variables as Thread local storage. However, `__thread` is a GNU
specific keyword which thus limits compatibility with other
toolchains (for instance IAR).
This PR intoduces a new macro `Z_THREAD_LOCAL` which expands to the
corresponding C11, C23 or C++11 standard keyword based on the standard
that is specified during compilation, else it uses the old `__thread`
keyword.
Signed-off-by: Daniel Flodin <daniel.flodin@iar.com>
For code clarity, remove unnecessary `return` statements
in functions with a void return type they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This provides memory mappings with the ability to be initialized in their
paged-out state and be paged in on demand. This is especially nice for
anonymous memory mappings as they no longer have to allocate all memory
at mem_map time. This also allows for file mappings to be implemented by
simply providing backing store location tokens.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
When content validation fails it is rather difficult to figure out the
cause if some meaningless byte mismatches another meaningless byte.
Let's store each memory location with its own virtual address so if a
mismatch occurs when reading it back it is obvious where it comes from.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add the ability to touch memory in the opposite direction from one loop
to the next so to exercize the LRU eviction algorithm.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Make sure k_mem_unmap() completes successfully on memory that is half
paged-out and such memory is no longer accessible afterwards.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This is part of a series of moving memory management related
stuff out of the Z_ namespace and into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The board defconfig forces CONFIG_USERSPACE to be disabled
due to small number of available MPU regions which are not
enough for userspace testing.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Also any demand paging and page frame related bits are
renamed.
This is part of a series to move memory management related
stuff out of the Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is part of a series to move memory management related
stuff from Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is part of a series to move memory management functions
away from the z_ namespace and into its own namespace. Also
make documentation available via doxygen.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This renames z_phys_map() and z_phys_unmap() to
k_mem_map_phys_bare() and k_mem_unmap_phys_bare()
respectively. This is part of the series to move memory
management functions away from the z_ namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rename all Silicon Labs radio boards to always use the official kit name of
the kit containing only the radio board as board target name. Disentangle
boards using Series 1 and Series 2 SoCs that have almost nothing in common
in terms of devicetree content, but still occupied the same directory.
As part of the initial HWMv2 port, all radio boards were merged into a
single target efr32_radio, using the SoC as a board qualifier to target
specific boards. This was unfortunate, as the SoC name is not sufficient
to identify a specific board -- the same SoC may be used on multiple
different boards. This commit reinstates every radio board as an individual
board target.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Adding bt_tester support.
Adding bt_tester app build
with Twister for frdm_rw612 board
Fix failing tests/samples due to unsufficent MPU ressources
by releasing unnecessary MPU regions.
Twister builds added on peripheral/central ht and
enabled Power manager on those examples to cover
the CI builds with PM enabled.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
This sets CONFIG_MAX_THREAD_BYTES to 3 as the tests need a few
more bits to build for board intel_adsp/ace30_ptl.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Make `struct arch_esf` compulsory for all architectures by
declaring it in the `arch_interface.h` header.
After this commit, the named struct `z_arch_esf_t` is only used
internally to generate offsets, and is slated to be removed
from the `arch_interface.h` header in the future.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Adding bt_tester support.
Adding bt_tester app build
with Twister for rd_rw612_bga board
Fix failing tests/samples due to unsufficent MPU ressources
by releasing unnecessary MPU regions.
Disable twister build on samples that are not meant to
be supported on this board, so exclude it from the test cases.
Update peripheral/central ht sample.yaml files
to test build for rd_rw612_bga.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
This uses the newly introduced CONFIG_MEM_DOMAIN_ISOLATED_STACKS
to determine whether to proceed with the tests to access other
threads' stacks. This provides more precise control on when to
run or skip these tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Disable the quadspi mpu region of the nucleo_f756zg (like done on
nucleo_f746zg) when testing the samples/userspace/shared_mem
or tests/kernel/mem_protect/userspace
The stm32f7 cortex M7 has 8 MPU regions and the one for quadspi prevents
the testcase to PASS.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This extends the test for memory mapped stack, as the address of
memory mapped stack object would be different than the actual
stack object.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adjustments of overlay and conf files to adjust for the MERGE removal.
The revert of MERGE requires specific overlay and conf files for boards
which relied on the MERGE feature.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
With memory domain enabled, all threads within the same domain
have access to each other threads' stacks, especially with
CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API enabled (as it is
expected behavior). So update the conditions to skip both
tests to read and write to other threads' stacks.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
