This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
This is the initial commit to support PINCTRL driver for Renesas RZ/T2L
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/N2L
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This device is included on Silabs SiWx91x series. The current driver is
able to manage "High Power" and "Ultra Low Power" pins.
Co-authored-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add support for pinctrl to cc23x0 SoC. Like for other TI SoCs,
a node approach is implemented (no grouping approach).
Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com>
Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The GPIO peripheral on Silabs Series 2 devices is responsible for
allocating analog buses to analog peripherals. Enable support for
this in the pinctrl driver. Since these bus allocations are not
digital pins, introduce a new property silabs,analog-bus for this
purpose.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Improve the documentation of the IOMUXC GPR binding so that it is
clear what the cells in the specifier space of "pinmux" space mean. And
change the names of the cells to be more appropriate. "offset" instead
of "pin" and "mask" instead of "function" describes more precisely what
the cells in the specifier mean.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- remove calculation of pinmux value for stm32 in device tree binding
documentation.
- stm32-pinctrl.yaml contains wrong calculation as can be compared to
#define STM32_PINMUX in stm32-pinctrl.h.
- stm32f1-pinctrl.yaml also contains different wrong calculation
compared to #define STM32F1_PINMUX in stm32f1-pinctrl.h.
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Silicon Labs Series 2 and newer devices do alternate function
configuration fundamentally differently from Series 0 and 1. Pin routing
is done in a centralized fashion in the GPIO peripheral, as opposed to
having ROUTE registers in every peripheral. The concept of alternate
function location numbers also does not exist, functions are directly
assigned to GPIOs by their port and pin number.
This commit adds a new pinctrl driver for devices that use DBUS. It fully
makes use of pinctrl design principles as outlined in the Zephyr
documentation. The previous driver hard-codes pin properties such as filter
and pull-up/down in the driver itself, while the new driver leaves this up
to the user as configurable DeviceTree properties. The previous driver has
hard-coded support for UART, SPI and I2C, while the new driver has generic
support for all DBUS signals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds the pinctrl driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add a pinctrl driver for Microchip MEC5 HAL based chips.
The driver removes the YAML enum "no change" property
value from the driver strength and slew rate properties.
Update the shared header file in mec soc common folder to
use a different Z_PINCTRL_STATE_PINCFG_INIT for MEC5.
Modifications to legacy MEC172x XEC PINCTRL will be in
a future PR.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
support the configurations which apply for LVDS pads
+ termination resistor
+ current reference control
+ rx current boost
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Instead of forcing users to provide this setting, allow to describe
which signals require CLOCKPIN enablement at device nodes. This is later
captured by the pinctrl macros and applied in the pinctrl driver. Note
that name has been adjusted to nordic,clockpin-enable to avoid confusion
with clock related settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
On new SoCs, certain pins need to enable the clock setting on the pin
for it to work properly. For now, this has been handled internally in
the pinctrl driver, however, it appears to be an instance-specific
property (e.g. UARTE/SPIM instances in the fast domain do not require
such setting). Move the configuration of this settings to DT, the best
place where to have instance-specific hardware settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
"RW pinctrl" is clearly SOC specific naming for an IP
that is not necessarily constrained to live on one SOC series.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/pinctrl directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add support of voltage control to Renesas PFC driver. Voltage register
mappings have been added to r8a77951 and r8a77961 SoCs.
Allow 'power-source' property for 'renesas,rcar-pfc' node. This property
will be used for configuring IO voltage on appropriate pin. For now it
is possible to have only two voltages: 1.8 and 3.3.
Note: it is possible to change voltage only for SD/MMC pins on r8a77951
and r8a77961 SoCs.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
ESP32 family pinctrl files are currently placed in hal_espressif.
Move to main branch as part of pinctrl dt-bindings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
