Timer driver using Microchip 32KHz based RTOS timer as the kernel
timer tick. The driver uses one of the 32-bit basic timers to
support the kernel's k_busy_wait API which is passed a wait
count in 1 us units. The 32-bit basic timer is selected by using
device tree chosen rtimer-busy-wait-timer set to the handle
of the desired 32-bit basic timer. If this driver is disabled,
the build system will select the ARM Cortex-M4 SysTick as the
kernel timer tick driver. The user should specify RTOS timer
as kernel tick by adding the compatible properity and setting
the status property to "okay" at the board or application level
device tree. The driver implements two internal API's for use
by the SoC PM. These two API's allow the SoC PM layer to disable
the timer used for k_busy_wait so the PLL can be disabled in
deep sleep. We used a custom API so we can disable this timer
in the deep sleep path when we know k_busy_wait will not be
called by other drivers or applications.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The new GRTC reading manner of the SYSCOUNTER uses hardware mechanism which
allows to keep it alive when any of CPUs is not sleeping. Otherwise
the SYSCOUNTER goes into sleep mode. Thus there is no
longer need to maintain the `CONFIG_NRF_GRTC_SLEEP_ALLOWED` symbol, however
if the user wants to have the SYSCOUNTER enabled all the time the
`CONFIG_NRF_GRTC_ALWAYS_ON` can be used instead.
The nrfx_grtc driver no longer provides the `wakeup-read-sleep` reading
manner.
Also setting the GRTC clock source is performed by the nrfx_grtc driver so
it has been removed from the `sys_clock_driver_init()` function.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This driver works both with native_posix and native_sim.
native_sim will eventually not set NATIVE_SIM_NATIVE_POSIX_COMPAT
(i.e. not pretend to be native_posix) so let's correct the
dependencies.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
GRTC needs to use direct clock source path instead of system clock path
to support ELV mode for nRF54L targets.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Currently function `z_nrf_grtc_wakeup_prepare()` should be available
only for the GRTC manager (`CONFIG_NRF_GRTC_START_SYSCOUNTER` is active).
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Add checks to return value of esp_intr_alloc to avoid drivers init
returning 0 when interrupt allocation fails.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The current driver implements the global defined "systick" interrupt
callback "sys_clock_isr" as a standard C function with an argument.
However, ARM's direct interrupt handlers do not have any arguments;
they must be declared as "void handler(void)".
Additionally, the direct handler should include some missing special
header/footer.
Fixes: #75693
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
Replace useless "TICKLESS" define by
IS_ENABLED(CONFIG_TICKLESS_KERNEL) one, and replace error-prone
'cycle_t' pseudotype defs by real typedefs.
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Fix timing in suspend-to-ram when using STM32WBA.
Switch to use RTC timer should be done only when idle is set
and LPTIM clocks should be switched off
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Changes to bring support for esp32c6 SoC.
- clock control
- gpio
- pinctrl
- serial
- timer
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
When both MCUBoot and application run, systimer is initialized twice.
As a consequence, application freezes as systimer new initialization
conflicts with previous.
This PR adds the systimer clock disable function, that shall be called
before mcuboot jump to application, making sure it will
work as expected.
Fixes#74189
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The reason is that this driver needs to call the function
'irq_connect_dynamic()' which is implemented with DYNAMIC_INTERRUPTS.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
TI Dual-Mode timer is used as the arch timer for systick on J721E R5
cores. Add DM Timer for systick timer support.
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
The original driver has two defects: 1. When setting the next timeout
value the original implementation simply sets a delta value equal to
ticks * CYC_PER_TICK. This operation is reckless and may incorrectly
"reset" the fractional tick, causing clock skew. 2. The original
implementation doesn't handle the counter overflow situation. When the
counter overflows from 0xffffffff to 0x0, the uptimer counter becomes
incorrect. We have fixed above issue by rewriting most of the functions in
this driver and verified it by running all tests under
tests/kernel/timer folder.
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Fix error due to compatible string changing in DT and
forgetting to update this driver with the change.
Also make the counter symbol hidden.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
These devices have a somewhat odd hybrid design, with a free-running
64 bit up counter but no comparator. Instead interrupts are triggered
by (one of an array of) 32 bit down counters with reset (a-la SysTick,
but without the 24 bit precision issues). The combination actually
results in a fairly simple driver as we can skip the comparator
rounding math.
Signed-off-by: Andy Ross <andyross@google.com>
This driver is impossible to make time-accurate using single-shot
mode. Time accuracy may be obtained only by using periodic mode, meaning
it is not tickless capable either. Let's simplify the code by only
supporting periodic mode and strip out the TSC stuff. Any hardware with
TSC capability should now use the apic-tsc driver instead.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.
This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Let's replicate a common code pattern for this to be abstracted more
easily in the future. In addition to duplicating the correctness fixes
implemented in the ARM and RISC-V drivers, this eliminates a couple large
runtime divisions.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The `z_nrf_grtc_timer_get_ticks()` function converts system ticks
to GRTC ticks. It gets the current system tick to calculate an
absolute GRTC value. The same does the test function to provide
an argument to be converted. If the system tick occurs between those
`sys_clock_tick_get()` calls the `z_nrf_grtc_timer_get_ticks()` will
take into account the newer tick while the test estimate bases on
the old tick value. Due to that the maximum result error is 1 system
tick minus 1 GRTC tick which equals (`CYC_PER_TICK` - 1) for GRTC
ticks.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This commit aligns the GRTC driver to changes introduced in
hal_nordic. Some of the features regarding GRTC sleep/wakeup
functionality has been modified and moved out to the nrfx
driver's code.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
When function sys_clock_set_timout() is called with small value
(i.e. 1) calculated time to be programmed to TIMER2 reload
register may be such that is expires before code set's it
up. In that case timer interrupt will be scheduled in far
future.
With this change, code checks after it sets reload value if
requested time already passed and if so TIMER2 interrupt
is marked as pending to avoid races.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
d599e2b670 removed early return from sys_clock_timeout_handler if
current counter value is less than cc_val. It seems that this return is
needed as after the removal some stress tests which were using system
timers heavily started to hang.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
We have already code using toolchain provided __get_cpuid(), clean up
apic_tsc and make it consistent with the rest of the code.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Misc fixes for the grtc timer driver:
* In non tickless mode:
* The tick time would drift a bit with each interrupt
* If something would cause a very significant delay
in handling the tick interrupt the number of announcements
would be incorrect
* Fortickless mode: The calculation of the next tick time
in sys_clock_set_timeout() was incorrectly done,
resulting in two spurious, too early, wakes of the kernel
before each correct wake. This caused tests/kernel/context/
to fail.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The code currently clamps timeout length so not to overflow the computed
cycle difference variable or the sys_clock_announce() argument's range.
But this completely fails to take into account the case where two
successive timeouts with enough time between them will still overflow the
cycle difference and/or the tick count.
Fix this by clamping the actual number of cycles to wait for based on
the previous report occurrence rather than clamping the timeout ticks.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
In commit 6068255512 ("drivers/timer/arm_arch_timer: Fix cycles
overflow with GDB stub") an extra TO_CYCLE_DIFF() macro was introduced
to bypass the cycle_diff_t type cast in some cases.
The actual fix consists in defining that type properly in the first
place. That's the very reason why such type was abstracted.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
There are two issues being fixed here:
1) The code currently clamps timeout length so not to overflow the
computed cycle difference variable or the sys_clock_announce()
argument's range. But this completely fails to take into account
the case where two successive timeouts with enough time between them
will still overflow the cycle difference and/or the tick count.
2) If a timeout with K_TICKS_FOREVER is provided then the comparator is
set with UINT64_MAX which is bogus. Not only this value doesn't make
much sense in the context of a running cycle counter, but it also
opens the possibility for the same cycle diff and/or ticks overflow
as above.
Fix both of those by clamping the actual number of cycles to wait for
based on the previous report occurrence rather than clamping the timeout
ticks.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
add support for retrieve clock frequency (HW clock cycle per sec) of
system timer at runtime by reading cpu clock via cpuid
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds timer driver for Renesas SmartBond(tm) family.
It uses TIMER2 block which is in PD_TIM power domain so it can work even
if ARM core is disabled, thus can work as a sleep timer.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Negative error codes cannot be returned if the function returns an
unsigned integer. Change function's API to return the read compare
register value through a pointer and the actual result as a signed
integer.
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Interrupt handlers are expected to have a pototype
void (const void*)
but nrfx_grtc_irq_handler has just a void(void)
(with no input parameter).
Fix it by using a trampoline.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The LL_APBx_GRPn_ReleaseReset clears reset bit in RCC,
however this bit is reset by default. Code that set
this bit was removed in previous commit
0856e99155
Keepint the autonomous clocks for STM32U5 family.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Add ability to set a wakeup counter in case OS Timer is
disabled in certain low power modes. Also add code to
compensate the tick value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
When running SOF on Intel ADSP we choose to only serve the timer
interrupt on the primary core.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit enhances the accuracy of hardware cycle calculation before
setting the IT8xxx2 event timer. The next target cycle is calculated by
the last, elapsed, and expected timeout ticks. And then, the difference
in hardware cycles between the target cycle and the current cycle is set
into the event timer. This increased accuracy effectively resolves the
clock drift issue.
Tested with:
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
-T kernel.timer.tickless
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_behavior
-T kernel.timer.timer
Fixes#67474#67833
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Include into compilation the nrfx_gppi_dppi_ppib helper and related
interconnect layers when DPPIC nodes are enabled in DTS. Provide macro
definitions required by those interconnect layers based on information
from devicetree (the nrf_grtc_timer is only modified because a macro
that it uses became more generic).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This was part of the mega hwmv2 commit. Looks like hpet drivers heavily
relies on soc.h. Reverting this for now while we look for a proper fix
and remove reliance on soc.h for drivers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When CONFIG_SYSTEM_SLOPPY_IDLE is not set, then system
can sleep for -1 means waking Up at the max possible
counter value (INT_MAX)
When CONFIG_SYSTEM_SLOPPY_IDLE is set sleeping K_TICKS_FOREVER
means never wakingUp
Signed-off-by: Francois Ramu <francois.ramu@st.com>
... in the related parts, so that the driver can be used on nRF54H20
where the clock control is not present yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Move code that prepares `NRFX_CONFIG_GRTC_*` definitions based on
information from devicetree from the nRF54L15 nrfx_config header
to the global one, so that the code can be used by nRF54H20, too.
The checks that validate owned-channels and child-owned-channels
DT properties are moved to the nrf_grtc_timer driver so that
the global nrfx_config is not polluted unnecessarily.
The default values in nrfx_config_nrf54l15_enga_application.h
are restored to those from the corresponding template file.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for a backup standby timer in STM32 LPTIM driver for cases
when the LPTIM is not available (ie standby low power mode).
A counter (typically RTC) is used for such a case.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove initialization of static variable to 0 to prevent resetting the
value when reinitializing the driver after resume from standby.
This has no impact since static variables are initialized to 0 by default.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that STM32_LPTIM_CLOCK choice symbol is defined from device tree,
remove the prompt which was defining it as a user selectable entry.
Remove the warning related to possible symbol misalignment with
device tree setting.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
In sys_clock_set_timeout(), input "ticks" is used to compute next
timeout point, Ambiq's STimer API used to sets next timeout has input
parameter as ui32Delta, which inside the API is using
"this value to add to the STimer counter and load into the comparator
register" according to its spec, thus the this delta clock is
almost equivalent to input "ticks"'s concept, and is not related to
last_count, it should be computed directly from input "ticks".
This correction fixes the test case failure at
zephyr\tests\kernel\tickless\tickless_concept.
Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
In init function, start timer with period CYC_PER_TICK if tickless is
not enabled, This change is for fixing the issue that disabling
CONFIG_TICKLESS_KERNEL the OS tick is not work issue, this
causes the OS not starting scheduling correctly.
Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
If GDBSTUB is enabled and the kernel runs in tickless mode, the timer
must not convert the delta cycles to a 32-bit data type (cycle_diff_t in
this case). The delta_ticks variable would overflow and the next timeout
would be set before the current timestamp, thus generating an interrupt
right after leaving the handler. As a result, the system would receive
tens of thousands of interrupts per second and would not boot.
Cc: Michal Sojka <michal.sojka@cvut.cz>
Signed-off-by: Marek Vedral <marek.vedral@gmail.com>
NRFX has introduced HALY software layer which is a superset of HAL
and aggregates some hardware registers manipulations in a single
function calls.
Quote from nrfx changelog:
"HALY is an extension of the HAL layer that aggregates basic hardware
use cases within single functions. Now it is used instead of HAL
in the corresponding drivers."
This commit zephyr's driver to be aligned with the approach used
in nrfx, where drivers has been switched to use HALY instead of HAL.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
With low LPTIM freq when prescaler is set to 16 or 32,
the CONFIG_SYS_CLOCK_TICKS_PER_SEC must be reduced to
LPTIM CLOCK_/prescaler to avoid spurious timer wakeup activity.
Assert error if the CONFIG_SYS_CLOCK_TICKS_PER_SEC
is not compatible with the lptim clock freq.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rename to LPTIM_PRESCALER, the <st,property> prescaler of
the stm32 LPTimer. This commit gives better readability than
LPTIM_CLOCK_RATIO.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
SysTick usually has higher measurement resolution than the IDLE timer.
When the time in low power mode is very short or 0, it is possible that
SysTick usually has measures more time since the sys_clock_set_timeout
than the idle timer.
Handle that case to keep uptime correct.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The idle timer has its max value and can overflow. We measure time passed
since the sys_clock_set_timeout call. Take possibility of the overflow
into account.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
When the idle timer is in use, we calculate number of cycles passed
since the sys_clock_set_timeout call.
The cycle counter can overflow easily, when the counter is 32-bit wide.
Handle that case.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Revert "drivers: timer: lptim timer clock on stm32u5 has a prescaler"
This reverts commit c14670abea.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Allow enabling the Cortex-m idle timer only if power management is set.
It doesn't make sense to use an idle timer without PM.
It allows adding the idle timer chosen node to dts without enabling the
idle timer by default. Now, the PM config has to be set as well.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The timer driver doesn't annouce/set the timeout at the tick boundary
but at the absolute next expiration time.
It will cause the accumatlation of the tick drift and cannot pass the
kernel/timer/timer_behavior test suite.
This commit fixes the tick drift problem by annouce the time at the tick
bouandry.
Fixes#59594
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Some chips, that use Cortex-M SysTick as the system timer, disable a
clock in a low power mode, that is the input for the SysTick e.g.
STM32Fx family.
It blocks enabling power management for these chips. The wake-up
function doesn't work and the time measurement is lost.
Add an additional IDLE timer that handles these functionality when the
system is about to enter IDLE. It has to wake up the chip and update the
cycle counter by time not measured by the SysTick. The IDLE timer has to
support counter API (setting alarm and reading current value).
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Let's make the nrf rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets
so the configuration matches in both cases.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
`last_load` is the full N cycles and `SysTick->LOAD` should
be loaded with `last_load - 1` for the calculations work
correctly.
Note: This only affects a kernel in ticked operation.
Tickless kernels periodically restart the timer correctly.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
The existing implementation did not properly
handle when `SysTick->VAL` is zero.
This caused three subtle edge cases:
* val1=0,COUNTFLAG=0,val2=0
This should result in no cycles elapsed,
however `(last_load - val2) = last_load`.
So an extra `last_load` cycles was returned.
* val1=0,COUNTFLAG=0,val2=(last_load-1)
This should result in 1 cycle elapsed,
however `val1 < val2` so an extra `last_load`
cycles was returned.
* val1=[2,1,0],COUNTFLAG=1,val2=0
This should result in `last_load` cycles elapsed.
However, `last_load * 2` cycles was returned.
To fix the calculation, val1 and val2 are first
wrapped/realigned from [0:last_load-1] to [1:last_load].
Tidy comments to better reflect the SysTick
behaviour and link reference manuals.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
The `SOC_NRF53_RTC_PRETICK` option is now allowed to be used with
`NRF_802154_RADIO_DRIVER`.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
The nrf53 pretick can be used with non-zero
`NRF_RTC_TIMER_USER_CHAN_COUNT` Kconfig option.
The nrf53 pretick requires just one RTC1 CC channel.
The nrf53 pretick handles also RTC1 and RTC0 both CCs and OVERFLOW
events by examination of events scheduled on them. The pretick is set
based on number of ticks to the closest event scheduled that can trigger
an interrupt.
Because the operation in `z_arm_on_enter_cpu_idle` hook would
take too much time with interrupts disabled, the
`z_arm_on_enter_cpu_idle_prepare` hook enabled by Kconfig option
`ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK` is used. It performs RTC0 and RTC1
examination, and sets pretick without interrupts being blocked.
The LDREX/STREX are leveraged to detect if exception took place
between start of `z_arm_on_enter_cpu_idle_prepare` and
`z_arm_on_enter_cpu_idle`. If exception has not been taken, the pretick
calculation can be trusted because source data could not changed and
too much time could not pass. Otherwise the sleep attempt is disallowed,
the idle will loop again and try later.
Prompt for `SOC_NRF53_RTC_PRETICK` Kconfig option allows to control
this option by an user and turn the feature off if necessary.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Add RTC pretick option that triggers HW activity one tick before and
RTC event that leads to the interrupt. Option is active only on nrf53
network core.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
