Add the ability to set the MAC address from the command line when
running a native sim build.
Signed-off-by: Ibe Van de Veire <ibe.vandeveire@basalte.be>
Only STM32F1X and STM32F2X are using the hal api v1,
both of these soc don't support ptp, so ptp support
for hal api v1 can be dropped.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
rewirte code and remove code that use internal phy functions.
A few Kconfig options got removed, that are now set by the
phy via the DT.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
It is already ensured in the fpga logic, that there is only one
interrupt per liteeth dev at a time. So we can remove the irq_lock on rx.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This patch adds a mutex for the eth_tx() function to prevent multiple
threads from calling the function at the same time.
Also remove the unneded irq_lock in that function.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Added support to get irq from dts node, because some platforms may
use multi-level interrupts, and the system INTID may not be connected
directly to interrupt controller.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs.
This patch adds a driver and device tree bindings for the Ethernet MAC
core and its MDIO controller.
The driver was tested on a RISC-V softcore in an FPGA design, with an
RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree
bindings match the device tree generated by Vitis hsi. Note that Vitis
generates one of the two included compatible strings depending on
version.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Return -ENOTSUP in phy_mii_cfg_link when a fixed-link configuration is set,
indicating that MDIO read/write operations are not supported.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Modified nxp_enet_phy_configure to handle -ENOTSUP returned by the PHY
driver, indicating a fixed-link setup. If -ENOTSUP is returned, a warning
is logged, and PHY configuration is skipped without causing initialization
to fail.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
-Update the ETH_STM32_HAL menu configuration to conditionally
select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X is enabled.
-Align Ethernet descriptors to 32 bytes for STM32N6 to ensure
efficient DMA operations and improve cache line efficiency
and overall performance
-Add RISAF configuration in eth_initialize function for STM32N6
series to set up master and slave security attributes
for the Ethernet peripheral.
-Ensure RISAF configuration is done before enabling
the Ethernet clock to maintain proper security attributes.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Allow to configure the preemtiveness of the ethernet rx-thread independent
of the traffic-class queue.
Signed-off-by: Cla Mattia Galliard <cla-mattia.galliard@zuehlke.com>
On Zephyr devices that has an Ethernet switch IC with the Zephyr device
connected to the CPU port, there aren't necessarilly any register to
check the link state on that port. If the check is kept on such devices,
Zephyr will believe the link disappears
CONFIG_ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS after last message was
received, until a new message is received. If the application tries to
send data while the link is considered gone, sending returns an error,
sometimes indicating that the interface is down.
It also seems conceptually meaningless to try determining link state on
such devices, since as long as both the microcontroller and the switch
IC is powered, the link should always be up.
This commit therefore introduces a new Kconfig to allow disabling the
entire checking of link state, so that on devices where there is no
relevant PHY register to read, the check can be disabled.
Signed-off-by: Ole Morten Haaland <omh@ixys.no>
Previously the net_linkaddr struct had pointers to the link address.
This is error prone and difficult to handle if cloning the packet as
those pointers can point to wrong place. Mitigate this issue by
allocating the space for link address in net_linkaddr struct. This will
increase the size of the net_pkt by 4 octets for IEEE 802.15.4 where the
link address length is 8, but there no increase in size if link address
is 6 bytes like in Ethernet/Wi-Fi.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
- Added definitions for LAN8742 PHY registers and bit masks
to support auto-negotiation.
- The function `eth_init_api_v2` requires the Ethernet interface
to be properly initialized. In auto-negotiation mode,
it reads the speed and duplex settings to configure
the driver accordingly.
- Implemented functions to get link state and configure speed
and duplex mode based on auto-negotiation results.
- Ensured proper initialization of semaphores and MAC configuration
for both auto-negotiation enabled and disabled scenarios.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Added the abililty to set the IPv4 addres, gateway and netmask from the
command line when running a native_posix build.
Signed-off-by: Ibe Van de Veire <ibe.vandeveire@basalte.be>
Adds a check, that the phy device in the device tree, referenced
by the phy-handle property, is enabled.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
* Sort includes by groups each alphabetically:
- standard lib
- zephyr
- private
* Move log registration to be after all includes.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Rename this driver to eth_native_tap, including renaming all its
options.
The old options remain until v4.4, but as deprecated.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
- Added macros `STM32_ETH_PHY_MODE` to determine
the PHY mode and speed from the `phy_connection_type`
property in the device tree.
- Updated the `eth0_data` structure to use `STM32_ETH_PHY_MODE`
for setting the media interface.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
This driver was deprecated and must be removed by Zephyr version
4.1 according to lifecycle/release guidelines.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This config was missed when converting from eth_mcux to nxp_enet driver,
re-add it and use new one instead of old one.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There were some driver bindings issues for the davicom dm8806 driver:
- Missing type for reg-switch binding
- Missing required: true for int/reset gpios
- Fix macro for reg-switch
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Calculate the EBO properly, so the total frame written to TX FIFO
does not exceed maximum Ethernet frame length.
Makes the TCP stack to work properly, otherwise packets > 1472 are dopped,
as they would be padded by 64 more bytes
and hence exceed maximum Ethernet frame size.
Signed-off-by: Maciej Panek <panekmaciej@outlook.com>
Refactors the code in adin2111_offload_thread
to improve its readability. Adds code to read RX FIFO
in OA mode until it is empty.
Signed-off-by: Maciej Panek <panekmaciej@outlook.com>
This commit adds basic support for KSZ8463/KSZ8463F chips to the
dsa_ksz8xxx.c driver.
These chips have limited register compatibility with other members
of the KSZ8XXX family - their registers are 16 bits wide as opposed
to the 8-bit registers supported by the driver for KSZ8794 and
KSZ8863. Following the general logic of the existing code,
the 16-bit registers of KSZ8463 are split into 8-bit halves.
For the KSZ8463F chip, it is assumed that both ports are used
in Fiber mode.
A new configuration option, CONFIG_DSA_KSZ_PORT_ISOLATING, has been
added to isolate traffic between DSA slave ports.
The driver has been tested on a custom board with an STM32F7 SoC.
Signed-off-by: Aleksandr Senin <al@meshium.net>
This is to support handling pseudo MAC during initialization, but not
to support DSA master port. Current driver supports DSA with limitation
that only switch function is available without management via DSA master
port. DSA master port support is TODO work.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
NXP i.MX NETC is a TSN capable Ethernet IP. It may support
ENETC MACs, or/and multiple ports switch.
The ENETC MAC was handled by eth_nxp_imx_netc driver.
This DSA driver is to support NETC switch device.
Current driver supports DSA with limitation that only switch
function is available without management via DSA master port.
DSA master port support is TODO work.
Take i.MX RT1180 NETC hardware as an example.
+--------+ +--------+
| ENETC1 | | ENETC0 |
| | | |
| Pseudo | | 1G |
| MAC | | MAC |
+--------+ +--------+
| zero copy interface |
+-------------- +--------+----------------+ |
| | Pseudo | | |
| | MAC | | |
| | | | |
| | Port 4 | | |
| +--------+ | |
| SWITCH CORE | |
+--------+ +--------+ +--------+ +--------+ |
| Port 0 | | Port 1 | | Port 2 | | Port 3 | |
| | | | | | | | |
| 1G | | 1G | | 1G | | 1G | |
| MAC | | MAC | | MAC | | MAC | |
+--------+-+--------+-+--------+-+--------+ |
| | | | |
NETC External Interfaces (4 switch ports, 1 end-point port)
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit fix the pin function configuration for mii and rmii
setting of Renesas RA8 ethernet driver
Correct pin function setting for mii is
PFENET = (uint8_t)(0x1 << R_PMISC_PFENET_PHYMODE0_Pos);
and rmii is:
R_PMISC->PFENET = (uint8_t)(0x0 << R_PMISC_PFENET_PHYMODE0_Pos);
Change code to intialize ping in driver init function, change
method of getting and checking via enum index of device tree.
Add build assert for invalid phy type.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
