Commit Graph

1256 Commits

Author SHA1 Message Date
Grant Ramsay
9df37fff79 drivers: serial: Add pinctrl support to the NS16550 driver
This enables configuring pins for the UART

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-03-02 13:50:06 +01:00
Nazar Palamar
f956e81bb6 drivers: serial: Add Infineon CAT1 UART driver
Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-03-01 11:44:57 +01:00
Gerard Marull-Paretas
27b73a116f soc: arm: nordic_nrf: replace NRF_DT_CHECK_PIN_ASSIGNMENTS
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-28 08:42:05 -08:00
Gerard Marull-Paretas
aa9df1abc0 drivers: serial: nrfx_uart/e: drop -pin support
UART/E driver will only support using pinctrl now.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-28 08:42:05 -08:00
Sylvio Alves
f1cc21a146 driver: uart: esp32s3: enable ESP32S3 uart interface
Includes additional SoC specific headers.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-02-27 19:41:33 +01:00
Jordan Yates
b83cf1f1ee drivers: serial: uart_rtt: fix multi-channel
Populate the `channel` index when constructing configuration structs for
secondary RTT channels. Originally missed in #27704.

Fixes #54955.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-02-25 06:55:58 -05:00
Grant Ramsay
f92dd6d357 drivers: serial: Name the NS16550 variant Kconfig choice
Naming this choice allows setting a default value in defconfig.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-02-24 18:11:56 +01:00
Goh Shun Jing
9ecfa4decc drivers: serial: uart_altera: add driver
Add driver for altera avalon uart core.

Signed-off-by: Goh Shun Jing <shun.jing.goh@intel.com>
2023-02-23 09:26:33 +01:00
Mulin Chao
809e63a91a driver: uart: npcx: add missing tx/rx interrupt enabled checks
When checking if any UART TX/RX IRQs are pending, the driver should also
consider whether these IRQs are enabled. Or we still get pending status
set even if the related interrupts are disabled.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-02-22 16:30:08 +01:00
Mulin Chao
dbc614ee10 driver: uart: npcx: avoid concurrency writing UFTCTL register
In order to avoid concurrency situation during writing UFTCTL register,
this CL adds critical sections to prevent the unexpected result if the
driver wants to set/clear bits of this register.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-02-22 16:30:08 +01:00
Andriy Gelman
4e13e6ada7 drivers: serial: xmc4xxx: Fix Kconfig help entry
The configurations are no longer hard coded for UART_0.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Andriy Gelman
30b11260be drivers: uart_xmc4xxx: Add async support
Adds async uart for xmc4xxx SoCs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Andriy Gelman
cfeaada65e drivers: uart_xmc4xxx: Change order of functions
This patch is in preparation of uart async support. There are no
functional changes. The patch changes the ordering of functions to
organize shared functions between async/interrupt driven in the same order.
Also move uart_xmc4xxx_init() so that a forward declaration can be
removed.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Andriy Gelman
3dac715569 drivers: uart_xmc4xxx: Split up tx/rx into separate service requests
In preparation for async support. In async uart, service requests are
forwarded to separate dma lines. This patch splits up tx/rx into
separate service requests to enable this.

Also put service request enable code into a separate function. Before,
the same code was generated for different uart devices.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Muhammed Ahmed
3f0fc7fe6b drivers: serial: Add PM support for UART MCUX
Adding PM support to uart_mcux by gating clock and disabling transmitter

Signed-off-by: Muhammed Ahmed <muhammed.ahmed@intel.com>
2023-02-19 20:56:16 -05:00
Ramon Aerne
a5e04ccd4a drivers: serial: rp2040: fix rpi pico address mapping
Address map used for config item `uart_dev` and `uart_regs` is
currently derived using the rpi hal macros `uart0` and `uart1`
which map to the same register address as given in the `reg` property
of the devicetree.

However, the sdk macro is generated using `uart##idx` which zephyr does
not necessarily map to uart0 or uart1.
This is, for example, the case when disabling uart0 with the devicetree
status "disabled"
and enabling uart1 for which then the idx==0 and not 1 which therefore
maps to the wrong controller address space.

This can simply be fixed by deriving the base address from
`DT_INST_REG_ADDR(idx)` instead

Signed-off-by: Ramon Aerne <ramon.aerne@axelera.ai>
2023-02-09 23:40:38 +01:00
Francois Ramu
7dff172519 drivers: serial: stm32 uart driver avoid LOG_WRN when going to sleep
When the LOG_WRN is used on stm32 uart driver it could block
execution : when pin state for sleep mode is not defined by the DTS
even if no error is raised, LOG_ msg is crashing when entering sleep mode.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-02-09 13:14:46 +01:00
Fabio Baltieri
20644536b9 uart: microchip: fix build error with PM_DEVICE=n
Fix a build error when the driver is built with:

CONFIG_PM=y
CONFIG_PM_DEVICE=n
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE_INPUT_EXPIRED=y

due to uart_xec_pm_policy_state_lock_get() and rx_refresh_timeout_work()
declared under different configuration options.

Fixes: 343d1919f1 "uart: microchip: add low power & wake support"
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-30 18:54:59 +00:00
Jay Vasanth
343d1919f1 uart: microchip: add low power & wake support
changes to support low power and wake support in microchip xec uart
driver. Add support for wakerx_gpio config in dts to select the wake gpio.
Configure for wake in PM_DEVICE_ACTION_SUSPEND state and clear
interrupt in wake isr. Also added support for
CONFIG_UART_CONSOLE_INPUT_EXPIRED

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-01-27 14:25:58 -05:00
Goh Shun Jing
5858cca8b8 drivers: serial: uart_altera_jtag: enhancement
implement uart poll in and interrupt driven api.

Signed-off-by: Goh Shun Jing <shun.jing.goh@intel.com>
2023-01-27 14:24:43 -05:00
Shawn Nematbakhsh
1d3fb5490f drivers: serial: Add support for OpenTitan serial UART
UART output confirmed to work in simulation.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-27 19:25:26 +09:00
Cyril Fougeray
51fa86bb98 drivers: exti: stm32: expose STM32_EXTI_LINE_NONE
Common STM32_EXTI_LINE_NONE for declaration and setting
of wakeup EXTI line when configured.

Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
2023-01-27 01:02:08 +09:00
Mulin Chao
5973a944af Revert "driver: uart: npcx: add missing tx/rx interrupt enabled checks"
This reverts commit 271b306.

In rare conditions, this commit causes the uart shell mechanism to
corrupt on Cros ec system. Revert this commit on upstream repo first to
avoid blocking the development. Will dig out why this symptom occurs
later.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-01-18 16:08:49 +01:00
Lucas Tamborrino
41b431a01a drivers: uart: esp32c3: Add async support
Add UART async support for ESP32C3

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-01-12 19:09:01 +01:00
Manuel Arguelles
415131c2e4 drivers: serial: rename S32 to NXP S32
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2023-01-04 16:51:38 +01:00
Dawid Niedzwiecki
4a2a512c11 drivers: serial: fix STM32 async uart driver
Fix a bug that causes not handling an IDLE line detection interrupt for
some STM chips, e.g. STM32F412. It impacts the async UART
communication - an information that data have been recieved is lost.

The issue occurs when the IDLE flag is set during handling another UART
interrupt, e.g Transmission complete. The ISR calls uart_stm32_err_check
function, which clears the noise error flag with LL_USART_ClearFlag_NE
without any additional checks. Unfortunately, clearing the noise flag
also clears the IDLE flag for some chips(an read to the USART_SR
register followed by a read to the USART_DR register for STM32F412
clears PE, FE, NF, ORE and IDLE flags), hence the ISR is not called
again for the IDLE event. The IDLE flag is no longer set.

Add checking the noise flag before clearing it.

Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
2023-01-04 10:33:49 +01:00
Marcin Szymczyk
6e5f432eee drivers: serial: nrfx: ifdef optional baudrates
Some baudrates are not supported in certain SoCs.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-28 10:38:09 +01:00
Declan Snyder
f2e0ac5c58 drivers: uart_mcux_flexcomm: Add runtime configure
Add uart_configure and uart_config_get functionality to
MCUX flexcomm driver to be able to dynamically configure
flexcomm uart at runtime.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2022-12-21 09:38:33 -06:00
Mulin Chao
271b306b2d driver: uart: npcx: add missing tx/rx interrupt enabled checks
When checking if any UART TX/RX IRQs are pending, the driver should also
consider whether these IRQs are enabled. Or we still get pending status
set even if the related interrupts are disabled.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-12-21 12:19:13 +01:00
Andrzej Głąbek
c984a343af drivers: uart_nrfx_uarte: Prevent re-enabling RX until UART_RX_DISABLED
Fix the driver so that after a call to uart_rx_disable() it does not
allow re-enabling RX until the UART_RX_DISABLED is generated (what
means that the disabling procedure is complete). Otherwise, it is
possible that the RXTO event from the previous RX is handled right
after a new RX is started, and the RX buffer pointer gets corrupted
in the `rx_flush()` function.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-12-21 11:47:34 +01:00
Erwan Gouriou
66d4c64966 all: Fix "#if IS_ENABLED(CONFIG_FOO)" occurrences
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-12-21 10:09:23 +01:00
Pawel Czarnecki
0095eed3a1 dts: uart: silabs: make peripheral-id optional
peripheral-id property should be eventually removed.
For now set it as optional and allow skipping the usage
in UART driver.

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2022-12-20 22:50:19 +01:00
Filip Kokosinski
9756766892 drivers: serial: uart_gecko: Make driver dependent on pinctrl
This commit adds a series of driver-related changes to
Gecko pinctrl.

Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-12-20 22:50:19 +01:00
Pawel Czarnecki
e8d3673c13 soc: arm: silabs: remove soc_gpio_configure wrapper
It would be better to use GPIO_PinModeSet() functions directly
in the drivers.

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2022-12-20 22:50:19 +01:00
Jiafei Pan
9d6bda0ec1 drivers: mcux_lpuart: fix compile warning
Fixed the following compile warnings:
../include/zephyr/sys/util.h:108: warning: "ARRAY_SIZE" redefined
hal/nxp/mcux/mcux-sdk/drivers/common/fsl_common.h:236: note:
this is the location of the previous definition

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-12-20 09:22:40 +01:00
Jiafei Pan
e8d3e7d544 drivers: mcux_lpuart: remove unsed soc.h
soc.h will not used anymore, remove it.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2022-12-20 09:22:40 +01:00
Ravik Hasija
22e2b004df drivers: serial: Add Driver for CDNS UART IP6528
Adding New Serial/UART driver for Cadence UART IP6528.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-12 12:19:35 -05:00
Duong Vu Nam
b24f4625f0 arch: support nocache for Cortex-R52
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.

Enable nocache in each driver use it.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Patryk Duda
1aebcec02f drivers: serial: Reset UART using RCC before initialization
In multi-image environment, after jump to the image we can have UART in
unexpected state. Reset UART to default state to make sure that UART is
initialized properly and won't cause system to crash or hang.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Filip Brozovic
c60e100ab3 drivers: serial: numicro: fix poll_in function
The poll_in function of the NuMicro UART driver was using the UART_Read
function from the Nuvoton HAL, which is blocking. Replace it with a
non-blocking implementation.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Filip Brozovic
617aa8cc65 drivers: serial: numicro: use pinctrl instead of hard-coded values
This commit enables the numicro serial driver to configure the UART
pins using the pinctrl API.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Grixa Yrev
4fe862e396 drivers: lpuart: enable rs485 mode
NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.

Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
2022-12-07 10:12:14 +00:00
Andriy Gelman
9b43e3ac0f drivers: serial: uart_xmc4xxx: Fix write to fifo with more than one byte
Currently only the first byte was written when pushing more than
one byte into the fifo.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-05 11:03:22 +01:00
Francois Ramu
e00f91da41 drivers: serial: uart driver for stm32U5 suspends dma channel
When DMA transfer is enabled on the stm32U5,
the UART Tx channel must be suspended before stopping.
This will let the on-going transfer ends properly

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-11-23 11:32:27 +01:00
Francois Ramu
0300b34cf0 drivers: serial: stm32 UART driver do not start Rx timer if null
This commit is optimizing the uart isr execution to avoid starting
the Rx timeout if it is null. In anycase the async_timer_start
function is checking the tiemout value. This will just save some
execution lines.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-11-23 11:32:27 +01:00
Francois Ramu
939b274507 drivers: serial: stm32 uart async is valid for stm32U5 serie
The UART_ASYNC is supported on the stm32U5 serie through the
GPDMA driver.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-11-23 11:32:27 +01:00
Andrzej Głąbek
595fbf9b97 drivers: uart_nrfx_uarte: Remove redundant HW_RX_COUNTING_ENABLED calls
Merge three adjacent `if (HW_RX_COUNTING_ENABLED(data))` blocks into
a common one.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-11-22 12:46:38 +09:00
Andrzej Głąbek
9628ecdc39 drivers: uart_nrfx_uarte: Fix call to HW_RX_COUNTING_ENABLED()
Since the macro references `data->async->hw_rx_counting`, it cannot
be called when `data->async` is NULL, and this could happen when the
PM_DEVICE_ACTION_RESUME action was requested for an instance that uses
the interrupt-driven API while for another instance that uses the
asynchronous API the hardware counting of bytes was configured.
Prevent this by calling the macro from a proper `if` block.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-11-22 12:46:38 +09:00
Jan Hilsdorf
a429528e3d drivers: serial: convert Zephyr constants to rpi-hal constants
rpi-hal function "uart_set_format" expects data width in the range
of 5..8. So I created a new function “uart_rpi_set_format” which
contains common parts of “uart_rpi_configure”.

Signed-off-by: Jan Hilsdorf <jan.hilsdorf@gmail.com>
2022-11-19 14:18:00 +09:00
Johan Hedberg
fcfff0633e drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup
Convert the ns16550 driver to use the new centralized runtime BDF lookup
of PCIe devices.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-16 11:18:43 +01:00