Add support for the Arduino GIGA board, an STM32H747XI based development
board in Arduino form factor, featuring external flash, SDRAM, Bluetooth
and WiFi.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
These are RT1060 based boards that use the flash for XIP, the bus
(nxp,imx-flexspi) lives under memc or flash. Declaring the flash as
"jedec,spi-nor" causes the SPI NOR driver to create an instance for it,
but then there's no bus and the build fails.
Dropping the spi-nor compatible seems to fix the problem.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add configuration for RM68200 MIPI display. This display
controller drives a 1280x720 LCD display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds driver for SmartBond TRNG peripheral that with separate
ISR an thread data pools.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
On M7 based STM32 boards, external SDRAM may be present and mapped in the
area 0xC0000000-0xDFFFFFFF.
According to ARMv7-M Architecture Reference Manual chapter B3.1
(table B3-1), this area is specified as Device Memory Type, with the
consequence that all accesses should be naturally aligned, otherwise
a hard fault will be triggered whatever UNALIGN_TRP status in the CCR reg.
To avoid this issue, when available, configure external SDRAM memory
regions as a MPU with RAM attribute.
Fixes#54670
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Microchip XEC devices specify GPIO pin using octal numbering and
organize pins in banks of 32. Chip documentation does not use
bank naming rather naming each pin by its octal number. This has
led to the developer having to calculate the bit position of a pin
in its 32-bit bank when a specifying the pin for GPIO usage. We
created a set of defines for all possible GPIO pins that specify
the DT GPIO bank name used in the chip level DTSI files and the
bit position in that bank.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This demonstates how to use the TI K3 pincrtl driver.
Previously UART0 only worked becuase U-Boot leaves it configured
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This board's documentation states the current configuration supports
Ethernet. However, the mac node was not enabled in devicetree.
This commit enables the mac node in devicetree.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
update MEC172x adc driver to support device PM.
Implement pm resume and suspend actions to put adc
pins in proper state for suspend and resume.
Notify kernel of busy when adc sampling is in progress.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Rework the Host Command support. It includes:
-change API to backend
-change a way of defining rx and tx buffers
-fix synchronization between the handler and backend layer
-simplify the HC handler
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Follow naming pattern in the subsystems(logging or shell) and name
the layer between generic handler and peripheral driver "backend".
The name doesn't suit that well to the SHI backend, because there isn't
SHI API itself and the SHI interface is used only for the host
communication. So the backend code includes the peripheral driver itself.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
This adds the runner arguments for dfu-util to the longan_nano board,
to allow flashing via DFU in addition to openocd.
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
Devicetree pinout was written according to datasheet,
but RX and TX were crossed because labels in the datasheet
are written from debug interface point of view.
However, it seems that flow control pins were not crossed.
Fixes#54768
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Move to using 'select SPI' instead of 'depends on SPI'
(see commit df81fef for more details)
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add the BackUp RAM to the nucleo_u575zi_q platform.
Change the filename for the .rst to index.rst like other platforms
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the implementation for the akm09918c magnetometer driver.
Additionally, add the appropriate node to the TDK robokit1 device
tree. In order to prevent regressions, add the sensor to the sensor
build_all tests and specific tests using an emulator.
Signed-off-by: Yuval Peress <peress@google.com>
PHYTEC phyCORE-AM62x is board is based on TI Sitara applications
processor, composed of a quad Cortex®-A53 cluster and a single
Cortex®-M4 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Upgrading Xtensa toolchain for intel ACE1X boards.
Newer Xtensa toolchains support only xt-clang driver so we are
forced to switch.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Add support for testing the onboard PCA9420 regulator on the RT685 EVK
to the regulator voltage test. Since the ADC can only record voltages up
to 1.8V, and some regulators cannot have all voltage ranges tested
without crashing the system, only LDO1 and LDO2 are tested in this
testsuite
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
On the RT685, the sys_reboot API does not function correctly. This is
due to the fact that the external flash must be reset at power on. In
order to configure the ROM to reset the flash, a OTP shadow register
can be programmed with the GPIO port and pin of the flash reset pin.
Program these bits at boot when the CONFIG_REBOOT symbol is set,
so that sys_reboot works as expected.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Now that MCUBoot supports 16 byte alignment, the 1 byte write mode
is no longer neccesary for the RT685. Partition sizes have been
reduced, as MCUBoot swap times are otherwise abnormally long.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update write alignment requirements and partition sizes for RT595 EVK.
Now that MCUBoot supports 16 byte alignment, the 1 byte write mode
is no longer neccesary for the RT595. Partition sizes have been
reduced, as MCUBoot swap times are otherwise abnormally long.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This board's documentation states the current configuration supports RNG
However, the RNG peripheral, and the HSI48 clock that the RNG depends
on, were not enabled
This commit enables the RNG and the HSI48 clock.
Verified with entropy test.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
In preparation for async support. In async uart, service requests are
forwarded to separate dma lines. This patch splits up tx/rx into
separate service requests to enable this.
Also put service request enable code into a separate function. Before,
the same code was generated for different uart devices.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
LEGACY_INCLUDE_PATH has been defaulting to "n" and marked as deprecated
in both v3.2 and v3.3. Drop the option entirely for v3.4.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
All nRF91 and nRF5340 boards (except the DKs)
should document a note stating that TF-M/_ns
is currently not supported.
Signed-off-by: Mia Koen <mia.koen@nordicsemi.no>
Yaml description for simulators should contain simulation_exec
telling which tool to use. nsim_em11d was missing this entry
causing twister to only build but not execute tests on this
platform. Value from other nsims was used.
Signed-off-by: Maciej Perkowski <Maciej.Perkowski@nordicsemi.no>
