When affinity routing is enabled for Non-secure state
( GICD_CTLR.ARE_NS is '1'), need to set routing information
for the SPI interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This adds new FPGA controller which allow to control FPGA chips.
FPGA controller has been created to enable bitstream loading
into the reprogrammable logic. It adds completely new API,
which enables to check status of the FPGA chip, power it on
or off and reset it.
Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Remove the locally MSI/MSI-X capabilities ID define and use the
newly introduced one from the PCI Code and ID Assignment
Specification Revision 1.11 document header.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add defines for all the PCI and PCIe capabilities from the PCI Code
and ID Assignment Specification Revision 1.11 document.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Extend the PCIe API to find Extended Capabilities in the PCI Express
Extended Capabilities located in Configuration Space at offsets 256
or greater.
Note: the Root Complex Register Block is not supported
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Position over LTE (PoLTE) can be used to locate a device as
an alternative to GNSS.
Increase RX thread stack size for PoLTE processing.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
Allow application control for starting modem driver.
This allows network attach to be randomized.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
For getting the address of the RAM region in the application we need to
extend the api for the flash_simulator.
This path introduce flash_simulator_get_memory() call which allow to
do so.
Signed-off-by: Sigvart Hovland <sigvart.m@gmail.com>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
This changes pci_msi_enable() to take IRQ number as a function
parameter. The old behavior relies on putting the IRQ number
into the interrupt line register in the PCI config space
during IRQ allocation, and reading it back when enabling IRQ.
However, the interrupt line register is only required to be
read-/writable when legacy interrupt is supported on the device.
Otherwise it has undefined behavior. On ACRN, they don't even
care about this register and always wires it to 0x00.
So this commit changes the behavior in pci_msi_enable() to not
require reading back the interrupt line register and instead
takes the IRQ number via function parameter.
Fixes#36765
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The magic code to identify context content is a 32-bit value
defined in the dma.h. When tested against the dma_context magic element,
both format must be aligned.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change so that num_completed_packets event handling is also
enabled for broadcast ISO only builds. This is because sending
data on a broadcast ISO still generates this event.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
STM32WL features a specific HSE clock with dedicated properties.
Add a dedicated binding and update STM32 clock control driver
header to take it into account.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
So far pcie_get_mbar() has been the only way to retrieve a MBAR. But
it's logic does not fit all uses cases as we will see further.
The meaning of its parameter "index" is not about BAR index but about
a valid Base Address count instead. It's an arbitrary way to index
MBARs unrelated to the actual BAR index.
While this has proven to be just the function we needed so far, this has
not been the case for MSI-X, which one (through BIR info) needs to
access the BAR by their actual index. Same as ivshmem in fact, though
that one did not generate any bug since it never has IO BARs nor 64bits
BARs (so far?).
So:
- renaming existing pcie_get_mbar() to pcie_probe_mbar(), which is a
more relevant name as it indeed probes the BARs to find the nth valid
one.
- Introducing a new pcie_get_mbar() which this time really asks for the
BAR index.
- Applying the change where relevant. So all use pcie_probe_mbar() now
but MSI-X and ivshmem.
Fixes#37444
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is the configuration of the stm32h723 where the
dma1 & dma2 of type V1 with a MUX. Even if DMA is of type V1,
the 'feature' does not exist with DMAMUX
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Clarify the PWM pwm_pin_set_cycles() function API details.
The API aims for synchronous (glitch-free) updates of the PWM period and
pulse width, but not all PWM controllers support this.
Similarly, the API aims for independance between channels on
multi-channel PWM controllers, but not all PWM controllers support this.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Change the behaviour of `lora_send` to block until the transmission
completes. The current asynchronous behaviour is exposed through the
new function `lora_send_async`. This naming convention brings LoRa in
line with other asynchronous subsystems.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add sensor API hysteresis attribute. This attribute allows for
configuring trigger threshold hysteresis values.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The timeout parameter for `lora_recv` is no longer a millisecond value
but a standard `k_timeout_t` value.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Fixup the doxygen comments for return values on `_dt` functions.
@retval should only be used when specifying actual return values,
@return is more general and can refer to other functions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Since the state is no longer modified by the device PM callback, just
use the state value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add variants of all i2c transfer functions that accept an `i2c_dt_spec`
as the bus specifier. This helps reduce code duplication in device
drivers.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Introduces the `struct i2c_dt_spec` type, which contains the complete
I2c bus information derived from devicetree. It serves the same purpose
as `struct spi_dt_spec` in that it can be constructed automatically in
`DEVICE_DT_INST_DEFINE` macros and provided as a single handle to I2C
API calls. While I2C has much less instance configuration than SPI, this
is still useful to enable the following pattern in device drivers that
support both I2C and SPI comms:
```
struct config {
union {
struct spi_dt_spec spi;
struct i2c_dt_spec i2c;
};
};
```
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Update doxygen usage of `@retval` to specify the value for each case,
instead of a chain of logic from the one `@retval`.
https://www.doxygen.nl/manual/commands.html#cmdretval
Convert `@retval`'s that simply reference another function to `@return`.
Convert some custom notes to `@note`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Microchip MCP7940N is a Real-Time Clock/Calendar. It operates on a I2C
bus. It can be used to set a calendar time and has two alarm channels.
When an alarm is asserted the state of the MPF pin of the MCP7940N will
change (depending on gpio active high/active low setting) to trigger an
interrupt.
Signed-off-by: Kieran Mackey <kieran.mackey@lairdconnect.com>
Add initial basic description for Cortex-M33 based
stm32u5 soc series.
This encompass description for base nodes, such as:
- cpu
- flash
- clocks
- sram
Additionally, provide description for variant stm32u575Xi.
Related to clocks nodes, added bindings for stm32u5 specific
rcc node as well as msi and pll clocks.
Header file stm32_clock_control.h was also updated to support
these new bindings.
Note that for compatibility with existing definitions, clock
node describing main pll clock, known as "PLL1", was given two
labels: "pll" and "pll1".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This driver supports the TI INA230 and INA231 Bidirectional Current
and Power Monitors. The devices work on the I2C interface and are
created from DT nodes with a compatible property matching "ti,ina23x".
The following datasheets were referenced while developing the driver:
https://www.ti.com/product/INA230https://www.ti.com/product/INA231
Twister passed:
twister -T tests/drivers/build_all/sensor/
Testing was performed on the stm32g071b_disco board with the following:
Load: ~170 ohms
Voltage: 5V
Measured Values:
Voltage: 5.1 V
Current: 0.032 A
Power: 0.157 W
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
The KBC/ACPI event data is 4-byte in width and composed of
event/data/type fields. However, the field position is defined by each
chip vendor via macro and not unified in the current implementation.
The commit uses the structure bit field to define and unify the field
position. It helps the application access it with a common approach.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
