When verifying sw_isr_table, take into account custom offset,
like `CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET` in some
RISC-V SoCs.
Relates to #71948 and #73232.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Add support for VPR CLIC to `nested_irq` kernel test.
Verified on nRF54L15 FLPR for now.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
`CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET` offsets IRQ in
vector table, align test to this functionality.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This commit updates the definition of z_shared_isr_table_entry
to use _isr_table_entry instead of specially created z_shared_isr_client.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
Updated the tests to use info from the devicetree or Kconfig as
ground truth and compare that with the output from the
functions under test.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Assert that the `local_irq` of each levels should only ranges
from `0` to `CONFIG_MAX_IRQ_PER_AGGREGATOR`, so that it doesn't
overflow the other aggregators.
Also, assert that the output of `z_get_sw_isr_table_idx` shouldn't
overflow the ISR table.
Update the `sw_isr_table` tests to test the range of
`CONFIG_MAX_IRQ_PER_AGGREGATOR` instead of the entire range of
level bits.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Split the `sw_isr_irq_parent_table` test into one that tests
the IRQ table index function which is generic and should
always be tested, and one that tests multi-instance -related
functions which only work in interrupt controller drivers that
has multi-instance implementation.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
`test_isr_dynamic` for `CONFIG_GEN_SW_ISR_TABLE=n` was somehow
overlooked in commit b7f1e98724.
I'm disabling the irq at the end of the test. The babblesim for the
`nrf5340bsim_*` target walked into a timeout otherwise.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
Relocate new and existing internal software-managed table
access functions from the public `sw_isr_table.h` into a
private header that should only be accessed internally.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Validate the following functions in the sw_isr_table:
- z_get_sw_isr_table_idx
- z_get_sw_isr_device_from_irq
- z_get_sw_isr_irq_from_device
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The test assumed that interrupt line 5 was up for grabs, but it
is not in general. (For ex., on an nrf53_bsim this is the clock
interrupt, which cannot be hijacked).
Instead, for boards that define it, let's use the int line
used for offloading SW interrupts (which is defined for all posix
arch boards in tree)
And if this is not defined, let's skip the test.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
When building this test with the armclang compiler we get the following
warning:
tests/kernel/interrupt/src/dynamic_isr.c
tests/kernel/interrupt/src/dynamic_isr.c:23:32: error: 'used' attribute
ignored on a non-definition declaration [-Werror,-Wignored-attributes]
extern struct _isr_table_entry __sw_isr_table _sw_isr_table[];
^
There is no need to add the __sw_isr_table on the extern, so remove it
to address the warning.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
qemu_x86 seems to take an extra instruction after the sti instruction
(irq_unlock) happens before it posts the interrupts. This can issues
if the instruction after the sti ends up reading the state that is
suppose to be updated by the ISR handler.
We see this behavior when building with LLVM. To workaround this issue
we add an arch_nop() to provide an extra instruction to allow the
interrupts to post.
Opened zephyrproject-rtos/sdk-ng#629 to track qemu issue.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move the direct interrupt test to tests/arch/x86/direct_isr. Two
reasons:
1. The direct interrupt is only for x86. It's arch-specific.
2. And it need extra gcc option to pass the build, that will
include testsuite number. Although it seems like we add a
extra testsuite for it, actually we can reduce whole tests
configuration in tests/kernel/interrupt. And also make this
test more generic as it used to be.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Every architecture must export the z_irq_spurious definition. Just unify
that in one single header file.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
change the test interrupt line number to a bigger one, because
the low number usually will be used by other devices.
Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There's no reason to wait a whole second here just to know if a tick
should have fired (though, yes, on some older/legacy/non-tickless
configurations, 128 ticks is actually more than a second).
Some simulators are very slow; busy waiting is expensive.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This PR include 2 changes to refine the testcases:
1. Now we using IPI to trigger interrupt in testing instead of INT
instruction, this means we don't need to hardcode the vector
number. That can avoid some problem.
Fixes: #40374
2. Refined the test cases. Tigger interrupt by INT instruction and
IPI cannot be masked by irq_disabled(). Unless it's a external
interrupt, such as a timer. Now remove those incorrect part of
these testcases.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
While reading the code, find typos in the code commits.
tests:kernel:interrupt:src:dynamic_isr, line 110 and 115.
Signed-off-by: Naiyuan Tian <naiyuan.tian@intel.com>
The default CONFIG_APIC_TIMER_IRQ_PRIORITY is 4, but it should be 1 for
ACRN. That's why the testcase failed due to no timer interrupt was
triggered.
And we also temporary adjust the testing IRQ for dynamic isr due to it
conflict with the IRQ of the APIC TSC deadline TIMER.
Fixes#36203.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Every va_start() currently triggers a FPU access trap if FPU is not
already used. This is due to the fact that va_start() must copy FPU
registers that are used for float argument passing into the va_list
object. Flushing the FPU context to its owner and granting access to
the current thread is wasteful if this is only for va_start(),
especially since in most cases there are simply no FP arguments
being passed by the caller.
This is made even worse with exception code (syscalls, IRQ handlers,
etc.) where the exception code has to be resumed with interrupts
disabled upon FPU access as there is no provision for preserving an
interrupted exception mode's FPU context.
Fix those issues by simply simulating the sequence of STR instructions
that the va_start() generates without actually granting FPU access.
We limit ourselves only to exception context to keep changes to a
minimum for now.
This also allows for reverting the ARM64 exception in the nested IRQ
test as it now works properly even if FPU_SHARING is enabled.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The interrupt offload testcases fail on some boards because the timing
of the delay is too short. Refine the testcases and make it not rely
on the delay timing.
Fixes#35097Fixes#35241
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Should not use -1 as an input parameter for unsigned int. Use zero
instead of -1 as invaild interrupt number to fix coverity warning.
Fixes#35146
CID: 235994
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Add test cases of direct interrupt for arch x86 and posix.
We register two direct interrupt at build time, then triggering
interrupt and check if ISR handler has executed or not. We also
check irq_enable and irq_disable works.
Why we add an extra compiler option "-mgeneral-regs-only" to make
it works in arch x86. because there might be some existing x87
instructions executing inside interrupt context.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Add test cases of regular interrupt for arch x86. This tests basic
functionailty of IRQ_CONNECT(), irq_enable(), irq_disable(),
irq_lock(), irq_unlock().
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Add 3 test cases to test offload job from isr, include:
1. test_isr_offload_job_multiple()
Validate the offloaded work executes immediately or not depends on its
priority, and it offloads to different k_work.
2. test_isr_offload_job_identi()
Validate the offloaded work executes immediately or not depends on its
priority, and it offloads to the identical k_work.
3. test_isr_offload_job()
Use dynamic interrupt instead of irq_offload() to verify the offloaded
work.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
This adds FPU sharing support with a lazy context switching algorithm.
Every thread is allowed to use FPU/SIMD registers. In fact, the compiler
may insert FPU reg accesses in anycontext to optimize even non-FP code
unless the -mgeneral-regs-only compiler flag is used, but Zephyr
currently doesn't support such a build.
It is therefore possible to do FP access in IRS as well with this patch
although IRQs are then disabled to prevent nested IRQs in such cases.
Because the thread object grows in size, some tests have to be adjusted.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The test_prevent_interruption() uses a key for the irq_lock(),
but the key has incorrect data type. This commit makes the key
unsigned int according to API docs.
Fixes#34023
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
The interrupt_util.h provides utils of trigger irq, now move them into
testsuite. All of the needed test cases can make use of them.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Improve dynamic interrupt test cases of interrupt for platform such as
x86, x86_64, native_posix, this improve code coverage of it.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Extend check to determine a usable ARM NVIC IRQ line to verify that the
IRQ line is not always pending.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
GICC_BPR has minimum legal values in secure and non-secure states.
'3' is the minimum BPR value leading to group and sub-group priority
as 'gggg.ssss'. In order to make an IRQ preemptible they need to
be in different priority group.
Hence to be generic priority values should be above '0x0f'.
IRQ0 - default priority (low prio)
IRQ1 - 0x0 (highest prio)
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit enables nested interrupt test for the Cortex-R platforms
that use the ARM Generic Interrupt Controller (GIC).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Kernel timeouts have always been a 32 bit integer despite the
existence of generation macros, and existing code has been
inconsistent about using them. Upcoming commits are going to make the
timeout arguments opaque, so fix things up to be rigorously correct.
Changes include:
+ Adding a K_TIMEOUT_EQ() macro for code that needs to compare timeout
values for equality (e.g. with K_FOREVER or K_NO_WAIT).
+ Adding a k_msleep() synonym for k_sleep() which can continue to take
integral arguments as k_sleep() moves away to timeout arguments.
+ Pervasively using the K_MSEC(), K_SECONDS(), et. al. macros to
generate timeout arguments.
+ Removing the usage of K_NO_WAIT as the final argument to
K_THREAD_DEFINE(). This is just a count of milliseconds and we need
to use a zero.
This patch include no logic changes and should not affect generated
code at all.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit enables nested interrupt test for the Cortex-A platforms
that use the ARM Generic Interrupt Controller (GIC).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
