Commit Graph

5 Commits

Author SHA1 Message Date
Mark Holden
7803a4e590 arch: riscv: ARCH_EXCEPT macro
Enable ARCH_EXCEPT macro for non-usermode scenario for RISC-V
Macro will now raise an illegal instruction exception so that mepc will
hold expected value in exception handler, and generated coredump can
reconstruct the failing stack

Coredump tests running on renode (for RISC-V) can now utilize fatal error
path through k_panic

Signed-off-by: Mark Holden <mholden@fb.com>
2022-01-01 07:38:20 -05:00
TOKITA Hiroshi
1421c1728b coredump: add support for Longan Nano boards
Longan Nano boards pass the test that with calling coredump().

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
Mark Holden
1a697ccf59 coredump: add support for RISC-V
This adds the necessary bits in arch code, and Python scripts
to enable coredump support for RISC-V

Signed-off-by: Mark Holden <mholden@fb.com>
2021-12-08 08:54:32 -05:00
Ioannis Glaropoulos
633a7208df tests: coredump: use undefined instruction to trigger CPU fault
When building the test for Cortex-M, use an undefined
instruction to trigger a CPU fault, instead of null
pointer de-referencing. That's because null-pointer
access may, in TrustZone-enabled platforms, lead to
a system crash (due to security violation).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-03-24 05:39:58 -04:00
Daniel Leung
86b2cbc5ea tests: add a test for coredump
This adds a simple test for coredump.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-08-24 20:28:24 -04:00