Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations
fixes#62956
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.
Converted manual bit shift/set/unset to use macros provided by
Zephyr.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.
The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Some NXP S32 shim drivers are using macros defined in
soc/arm/nxp_s32/*/soc.h but not including soc.h. Those still
can be built because the header file is included indirectly
by some other header files. This is very fragile, it should
be included directly
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.
Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Remove the HWSEM locking around stm32_exti_disable().
The STM32 EXTI driver uses the core-local interrupt mask regsiters on
STM32H7x7 asym. dualcore MCUs. There is no need to lock the HWSEM
guarding the EXTI when accessing these registers.
Some sensor drivers toggle their interrupt mask every time the sensor
triggers the IRQ line. Locking the HWSEM fails e.g. in situations where
one coprocessor serivces the sensor and the other coprocessor sets up
its interrupts initially during bootup. This prevents the sensor driver
from locking the HWSEM and causes a kernel panic on the corresponding
CPU.
Note: The opposing stm32_exti_enable() was already correctly without
locking.
Signed-off-by: Martin Gritzan <martin.gritzan@gmail.com>
Introduce an interrupt controller for the NXP S32 WKPU peripheral
that can be integrated with GPIO to trigger interrupts through
external interrupt pad inputs.
WKPU can trigger interrupts from certain input pads that support this
function, as well as wake-up events to the power management domain. This
patch only adds WKPU functionality as an interrupt controller to extend
the number of input pads that can interrupt the core. Power management
functionalities are not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.
Updated devicetrees that has PLIC accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Removing the edge-trigger Kconfig as it is supported by default
in the RISCV PLIC specifications.
Define the edge-trigger register offset in the driver instead
of retrieving the value from devicetree as it is not something
configurable. The value 0x1080 is defined in Andes & Telink
datasheets.
Updated build_all testcase.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT, so
don't try to select the symbol if not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert DEVICE_DEFINE to DEVICE_DT_INST_DEFINE, this allows the build
system to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Adjust some DT_INST macro as well while at it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Fix an incorrectly declared compatible and adjust some DT macros as
well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit follows the parent commit work.
This commit introduces the following major changes.
1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
to the 'include/zephyr/arch/arm' directory.
2. Change the path string which is influenced by the changement 1.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Use DEVICE_DT_INST_DEFINE instead of DEVICE_DEFINE to declare the device
structure. This ensures that the device gets an ordinal and is
initialized before any device depending on it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The old acpi implimentation is replaced with acpica interface
and updated x86 arch porting with the new interface.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Add TI VIM (Vectored Interrupt Manager) interrupt controller support.
VIM is a TI specific custom interrupt controller for ARM cores.
In J721E soc, VIM aggregates interrupts to Cortex R5 cores.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
VIM: section 6.3.3.6
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
As per #26393, Local APIC is using Kconfig based option for
the base address. This patch adds DTS binding support in the driver,
just like its conunter part I/O APIC.
Signed-off-by: Umar Nisar <umar.nisar@intel.com>
GIC-600 and later interrupt controllers have an additional
GICR_PWRR register that controls the power up sequencing
of the redistributors. Added logic to gicv3_rdist_enable to
configure GICR_PWRR if required.
Signed-off-by: Chad Karaginides <quic_chadk@quicinc.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following #60410, the NXP S32 external interrupt controller device
initializes after the core interrupt controller. Bump the NXP S32 intc
init level to initialize after the core intc and before the GPIO
device driver.
Fixes#61218
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Some architectures such as RISC-v support more than 255 interrupts
per aggrigator. This diff adds the ability to forgo the aggrigator
pattern and use a configurable number of bits for multilevel
interruts.
Signed-off-by: Joshua Lilly <jgl@meta.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The intc_gicv3_its driver is currently initializing in POST_KERNEL, but
PCIe device nodes depends on it and are initialized earlier. Change the
init level to PRE_KERNEL_1 to sort that out, and also put the driver in
line with other interrupt controller drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
SIUL2 may require multiple interrupt handlers instead of a single one as
currently supported for S32Z/E. This is needed to enable support on
S32K3.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Usage of 64-bit address constants from devicetree without
an UINT64_C wrapping macro results in the following warning
and the cut-off of the address value:
"warning: integer constant is so large that it is unsigned"
This change fixes such issue for PLIC, MTIMER and UART in case
they are used with some 64-bit RISC-V platforms
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
Currently, only the presence of a GIC is reflected in the device tree,
and its version must be set separately in each SoC's Kconfig.
This patch adds separate bindings for each GIC version whose presence
in the device tree automatically enables the corresponding Kconfig symbol.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
add explicit boolean type to 'if' statement controlling expression,
consolidating it with 'stm32_exti_is_pending' function return type, thus
improving code readability and maintainability, complying with required
[misra-c2012-14.4] rule which states; The controlling expression of an
if statement and the controlling expression of an iteration-statement
shall have essentially boolean type.
Found as a coding guideline violation (Rule 14.4) by static code
scanning tool.
Note: Tested on STM32L5 Nucleo-144 board (stm32l552xx).
Signed-off-by: ferar alashkar <ferar.alashkar@gmail.com>
add an unconditional break to switch-clause's default case, complying
with required [misra-c2012-16.3] rule which states; An unconditional
break statement terminate every switch-clause.
Found as a coding guideline violation (Rule 16.3) by static code
scanning tool.
Note: Tested on STM32L5 Nucleo-144 board (stm32l552xx).
Signed-off-by: ferar alashkar <ferar.alashkar@gmail.com>
1. use 'BIT' macro instead of explicit left shift operations, since
'BIT' macro implicitly adds unsigned type suffix, avoiding possible
[shiftTooManyBitsSigned] scenarios, and
2. add an explicit uint32_t cast to 'BIT' macro argument, complying with
required [misra-c2012-10.1] rule which states; operands shall not be of
an inappropriate essential type.
Found as a coding guideline violation (Rule 10.1) by static code
scanning tool.
Note: Tested on STM32L5 Nucleo-144 board (stm32l552xx).
Signed-off-by: ferar alashkar <ferar.alashkar@gmail.com>
Compiling previous code using LLVM reveals that accessing line_range
values in runtime is not clean, as the following error is generated:
"error: initializer element is not a compile-time constant"
Replace runtime method by compile time using UTIL_INC and UTIL_x2
macros.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
