Commit Graph

54 Commits

Author SHA1 Message Date
Flavio Ceolin
8100871856 soc: intel_adsp: Avoid duplicate adsp_memory_regions
This header is the same for all ACE platforms. Move it
a common folder.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-07 09:52:42 +02:00
Flavio Ceolin
6069f946be soc: intel_adsp: Avoid duplicate header
adsp_memory.h is pretty much the same for all ace platforms.

Generalize it getting register address from devicetree and
and move it to a common place.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-07 09:52:42 +02:00
Peter Mitsis
0bcdae2c62 kernel: Add CONFIG_ARCH_HAS_DIRECTED_IPIS
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.

As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.

Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases.  These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2024-06-04 22:35:54 -04:00
Kai Vehmanen
6ad9b6ccab soc: intel_adsp: tools: add intel_adsp_ace30 support to cavstool.py
Add support for intel_adsp_ace30 platforms into cavstool.py.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-06-04 14:03:32 -05:00
Flavio Ceolin
adabe57f4d soc: intel_adsp/ace: Fix SOC_TOOLCHAIN_NAME symbol
Set the appropriated toolchain name for each ace target.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 13:40:04 +02:00
Anas Nashif
d35a2b89f3 intel_adsp: dmic: enable support for ptl use new headers
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-06-04 13:40:04 +02:00
Flavio Ceolin
9637b8b0bc intel_adsp: ace30: Bring up ACE 3.0 (PTL)
This commit adds definition of ACE 3.0 Panther Lake board.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 13:40:04 +02:00
Kai Vehmanen
1541fe9e2f intel_adsp/ace: power: fix address space annotation for powerdown
power_down() expects a cached pointer. Fix the sparse annotation
to match the implementation (sys_cache_cached_ptr_get() returns a cached
pointer so this is correct).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-06-03 16:07:28 -04:00
Mathieu Choplain
8aa6ae43ce llext: add support for SLID-based linking
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.

SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
 * linking is faster because the comparison operation to determine
   whether we found the correct symbol in the export table is now an
   integer compare, instead of a string compare
 * binary size is reduced as symbol names can be dropped from the binary
 * confidentiality is improved as a side-effect, as symbol names are no
   longer present in the binary

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-06-03 15:29:34 -04:00
Kai Vehmanen
5a7600bec6 soc: intel_adsp: tools: add shell support to cavstool.py
Create a pseudo-terminal to access Zephyr shell on the audio DSP.
The shell terminal is enabled with "-p" command-line option.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-31 08:07:03 +02:00
Kai Vehmanen
6509b8199b shell: add shell backend for audio DSP using shared memory window
Add a new shell backend implemented over a shared memory window
on the Intel audio DSPs. The implementation uses the Zephyr winstream
to manage the data streaming.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-31 08:07:03 +02:00
Kai Vehmanen
db00b813f0 soc: intel_adsp: tools: align code style in maps_regs()
Cosmetic change to align code style when initializing DSP registers. The
code in intel_is_ace() branch was moved as-is from acetool.py when the
two tools were merged to make reviewing easier. Fix the code style to be
coherent in the merged cavstool.py. No functional change.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-29 10:47:29 -07:00
Kai Vehmanen
44dd5a4da9 soc: intel_adsp: tools: fix ace20 fw load flow
Use the correct register to read ROM status on intel_adsp_ace20.

Without this this fix, firmware load is successful but
boot takes extra 2 seconds and following warning was emitted:

WARNING:cavs-fw:Load failed?  ROM_STATUS = 0x0

The log-only mode (-l) was not working at all and is fixed
by this commit.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-29 10:47:29 -07:00
Nicolas Pitre
3c2e57c923 drivers/timer/apic_tsc: use ICR as a fallback timeout event source
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.

This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-05-29 08:40:43 +02:00
Yong Cong Sin
bbe5e1e6eb build: namespace the generated headers with zephyr/
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.

Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.

Updated the includes path of in-tree sources accordingly.

Most of the changes here are scripted, check the PR for more
info.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-28 22:03:55 +02:00
Kai Vehmanen
fa798ce2d5 soc: intel_adsp: only implement FW_STATUS boot protocol for cavs
The software protocol to write status value of 0x05 (FW_ENTERED)
into memory window 0 at Zephyr boot, is not needed in the ace1.x
boot flow and does not match the semantics host systems are expecting
at this location in the memory window (e.g. write of 0x05 is not
expected).

Make this logic specific to intel_adsp_cavs platforms and move the code
out from common intel_adsp code.

This commit depends on update to cavstool.py to use correct
ROM status register to observe boot state.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-27 08:16:10 -07:00
Kai Vehmanen
8fc76f1b6d soc: intel_adsp: tools: improve FW boot handling on ace1.x
Starting with ace1.x, the boot status is no longer reported by
the boot ROM in the SRAM status window as it was done in older
platforms. The current cavstool.py code works on these newer platforms,
as Zephyr soc bootcode writes to same location, but this is not
the recommended boot flow.

Modify boot flow to use a dedicated register to observe boot
state. This change improves usability of cavstool.py on ace1.x
platforms as:
 - it is possible to start cavstool.py (e.g. in log-only or shell mode)
   while DSP has been already been booted, but is currently in
   low-power mode (and SRAM window is not accessible from host)
 - more reliable boot and better error reporting as actual ROM
   status is observed

Furthermore, this change allows to remove the memory window
writes from Zephyr intel_adsp boot_complete(). This IPC interface
is application and IPC revision specific and the write should not
be done in generic Zephyr SoC code. However, to keep cavstool.py
working, the tool has to be updated first.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-27 08:16:10 -07:00
Flavio Ceolin
5ca3bc92c8 intel_adsp: power: SoC restores the clock
The SoC restores the clock only when leaving soft-off only.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-27 02:10:03 -07:00
Flavio Ceolin
f54232e912 intel_adsp/ace: power: Do not re-implement cache func
Do not re-implement a function to get a cached pointer. Zephyr cache
API already provides it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin
b496d0e52d intel_adsp/ace: pm: Remove unnecessary cache flush
soc_cpus_active is not in cached memory.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin
c335cb542c intel_adsp/ace: pm: Keep irq locked until restore context
Keep interruptions locked until we properly restore the core
context.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin
e728adffd2 intel_adsp/ace: pm: Remove unnecessary cache flush
core_desc is not located (nor is accessed) in cached memory.
There is no need to flush it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin
301055dec0 intel-adsp/ace: pm: Only core 0 can d0i3
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.

Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Kai Vehmanen
991b3623b0 soc: intel_adsp: ipc: don't call k_sem_init() multiple times
k_sem_init() is called for every IPC message sent in
intel_adsp_ipc_send_message(). This has not had any side-effects
in upstream configurations, but has been linked to a failing
run of test_obj_tracking_sanity test case in downstream Zephyr
use.

Replace k_sem_init() with k_sem_reset() as this is more appropriate
API to reset the semaphore count, and ensure deterministic
behaviour in case a thread is waiting on the semaphore at time
of reset.

Suggested-by: Peter Mitsis <peter.mitsis@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-23 11:50:50 -04:00
Adrian Warecki
369a3a1675 soc: intel: adsp: tgl: ace: Set correct virtual memory size
Corrected virtual memory size to match the range supported by the
Translation Lookup Buffer. The TLB size is 16 MB, however the first 128 KB
is dedicated to LPSRAM and bypasses the TLB. This was taken into account in
KERNEL_VM_BASE, so KERNEL_VM_SIZE was reduced accordingly.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2024-05-21 18:43:37 +02:00
Kai Vehmanen
0ca7ef78bc soc: intel_adsp: tools: merge cavstool.py and acetool.py code
Merge codebases of cavstool.py and acetool.py as the two have
a lot of duplicated code.

To ease with transition, keep acetool.py around with implementation
imported from cavstool.py. This will help to keep any automated
testing flows working that assume both tools exist.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-19 10:56:37 +03:00
Nicolas Pitre
57305971d1 kernel: mmu: abstract access to page frame flags and address
Introduce z_page_frame_set() and z_page_frame_clear() to manipulate
flags. Obtain the virtual address using the existing
z_page_frame_to_virt(). This will make changes to the page frame
structure easier.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-05-13 16:04:40 -04:00
Kai Vehmanen
2dd648698f soc/intel_adsp: ipc: initialize semaphore in driver init
The ipc driver device data (struct intel_adsp_ipc_data) contains a
semaphore. Upon device init, the device data is zeroed out. This is safe
for other fields, but the semaphore should be properly initialized
before use.

This lack of initialization leads to a system crash when CONFIG_POLL is
enabled (e.g. to enable CONFIG_SHELL), IPC driver handles an interrupt
and executes k_sem_give() on a uninitialized semaphore object. This will
eventually lead to null dereference in z_handle_obj_poll_events().

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-06 22:51:06 +01:00
Damian Nikodem
6205f82d4f intel_adsp: adsp_memory: update mtl memory definitions
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.

Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
2024-05-01 10:31:52 +02:00
Damian Nikodem
6fe16960fd intel_adsp: adsp_memory: update lnl memory definitions
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.

Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
2024-05-01 10:31:52 +02:00
Damian Nikodem
2176ca9f9b intel_adsp: adsp_memory: update cAVS 2.5 memory definitions
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.

Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
2024-05-01 10:31:52 +02:00
Najumon B.A
b5917146d4 soc: x86: add gpio acpi resource enumeration
add support for enumerate gpio resource using acpi

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2024-04-22 06:50:38 -07:00
Kai Vehmanen
7fd0a7a5eb soc: intel_adsp: replace icache ISR workaround with custom idle solution
A workaround to avoid icache corruption was added in commit be881d4cf2
("arch: xtensa: add isync to interrupt vector").

This patch implements a different workaround by adding custom logic to
idle entry on affected Intel ADSP platforms. To safely enter "waiti"
when clock gating is enabled, we need to ensure icache is both unlocked
and invalidated upon entry.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-04-15 16:26:39 +02:00
Flavio Ceolin
8a63a0a563 intel_adsp: ipc: Fix policy state lock usage
IPC has inverted the usage of the state lock API.
In this API semantics, the get method disallow the policy of
using the given state, while the put() release this constraint.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-04-11 09:07:13 +02:00
Kai Vehmanen
7fee1bdd39 soc: intel_adsp: cavs: fix power_down documentation
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-04-10 15:55:21 +02:00
Kai Vehmanen
03057f33d4 soc: intel_adsp: ace: fix power_down documentation
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-04-10 15:55:21 +02:00
Flavio Ceolin
e85226fd1a soc/intel_adsp: ipc: Remove fragile device state check
Checking if the device state is locked is not correct, device runtime
put / get is no longer checking for it and the only place that was
locking device's state was the pm action callback and if the idea
was to protect some concurrent call, using it is not enough.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-04-09 20:11:48 +02:00
Flavio Ceolin
741bbaca6d soc/intel_adsp: ipc: Remove unnecessary device state lock
There is no needed to lock/unlock a device state in its pm action
callback. The power management subsystem should take care of
serialize these calls.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-04-09 20:11:48 +02:00
Tomasz Leman
d5897a48aa ipc: intel_adsp: Ensure IPC completion before runtime idle
Prevent the system from entering runtime idle state during IPC
transactions until the HOST acknowledgment is received.

This patch modifies the IPC mechanism to:
- Lock the runtime idle state immediately after sending an IPC message
  to the HOST, preventing the system from entering a low-power state.
- Unlock the runtime idle state once the IPC transaction is acknowledged
  by the HOST, allowing the system to enter low-power states if
  conditions permit.

The changes ensure that the DSP does not enter a power state that could
interrupt the IPC communication process, maintaining the integrity of
the IPC state machine.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-04-09 16:58:24 +02:00
Flavio Ceolin
688fbb53ae intel_adsp: ace: Fix sparse error
Fixes the following errors when sparse (SCA) is enabled:

soc/intel/intel_adsp/ace/power.c:46:12: warning:
    cast removes address space '__cache' of expression
/soc/intel/intel_adsp/ace/power.c:48:9: warning:
    incorrect type in argument 1 (different address spaces)

Fixes #70725

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-03-29 17:20:57 -05:00
Daniel Leung
b69d2486fe kernel: rename Z_KERNEL_STACK_BUFFER to K_KERNEL_STACK_BUFFER
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-03-27 19:27:10 -04:00
Daniel Leung
6ea749de52 arch: rename arch_start_cpu() to arch_cpu_start()
Rename arch_start_cpu() to arch_cpu_start() so it belongs to
the "cpu" namespace.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-03-25 09:58:35 +00:00
Marcin Szkudlinski
3fde2c50c6 tracing: add intel ADSP memory window backend
This commits adds a tracing backend based on
Intel ADSP debug memory window

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2024-03-25 09:33:41 +01:00
Flavio Ceolin
6b9d01f995 intel_adsp/ace: power: No pending transaction before power gate
Issue an upstream read transaction through uncached memory to flush
out all pending transactions before power down the host domain.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-03-22 21:29:33 -04:00
Tomasz Leman
4ea52bdd12 soc: xtensa: intel: Update power status bitfields for LNL
This patch updates the power status register bitfield definitions in the
power management header for the Intel ADSP ACE 2.0 LNL platform.

Modifications include:
- Adjusting the 'ioxpgs' field from 4 bits to 2 bits.
- Adding a 'rsvd11' field with 2 bits to reflect reserved space.
- Changing the 'mlpgs' field from 2 bits to 1 bit.
- Updating the 'rsvd14' field from 1 bit to 2 bits for alignment.

These changes ensure that the power status register bitfields match the
latest hardware specification for the ACE 2.0 LNL SoC, which is crucial
for accurate power domain status monitoring.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-03-19 14:54:29 +01:00
Kai Vehmanen
010f39a409 soc: intel_adsp_cavs: store PS when power gating secondary core
When non-primary core is powered down and restart with sequence of:
 - PM state set to SOFT_OFF
 - once target core is idle, cut power with soc_adsp_halt_cpu()
 - power up core again with k_smp_cpu_resume()

The execution will continue from stored DSP core context, but
will hit an assert in z_smp_cpu_mobile() as the PS.INTLEVEL
is zero.

Fix this issue by storing and restoring PS register in this flow.

Link: https://github.com/zephyrproject-rtos/zephyr/issues/70181
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-03-15 18:16:51 -04:00
Serhiy Katsyuba
41b3c71586 drivers: dma: intel_adsp_hda: Fix L1 exit condition
Transition to a low power DMI L1 state should be allowed only after all
pending DMA channels transfers have started.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2024-03-15 08:59:12 +01:00
Flavio Ceolin
07426a800c intel_adsp/ace: power: Lock interruption when power gate fails
In case the core is not power gated, waiti will restore intlevel. In
this case we lock interruption after it.

In the bug scenario, the host starts streaming and via SOF APIs, keeps a
lock to prevent Zephyr from entering PM_STATE_RUNTIME_IDLE. During the
test case, host removes this block and core0 is allowed to enter IDLE
state.

When core0 enters power gated state, interrrupts are left enabled (so
the core can be woken up when something happens). This leaves a race
where suitably timed interrupt will actually block entry to power gated
state and k_cpu_idle() in power_gate_entry() will return. This is rare,
but happens often enough that the relatively short test plan run on SOF
pull-requests will trigger this case.

Fixes #69807

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-03-12 15:12:57 -05:00
Guennadi Liakhovetski
0a6e90b3b8 xtensa: make assembly-called functions static
z_mp_entry() and power_gate_exit() are only called from assembly code
in the same file, where they're defined. Make them "static" and add
an attribute to let the compiler know, that they aren't unused.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-03-11 14:26:06 +01:00
Daniel Leung
223e81b968 soc: intel_adsp/ace: use CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS
This enables the use of CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS to
specify how many NOPs for arch_spin_relax(). This is to keep
the atomic_cas() (via s32c1i) from saturating the internal bus
with contant RCW ops. The numbers should be further tuned
for specific application but these should provide a good start.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-03-08 18:04:18 +01:00