Mark the old time conversion APIs deprecated, leave compatibility
macros in place, and replace all usage with the new API.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Re-run with updated script to convert integer literal delay arguments
to k_thread_create and K_THREAD_DEFINE to use the standard timeout
macros.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Disabling SMP mode for certain tests was a one-release thing, done to
avoid having to triage every test independently (MANY are not
SMP-safe), and with the knowledge that it was probably hiding bugs in
the kernel.
Turn it on pervasively. Tests are treated with a combination of
flagging specific cases as "1cpu" where we have short-running tests
that can be independently run in an otherwise SMP environment, and via
setting CONFIG_MP_NUM_CPUS=1 where that's not possible (which still
runs the full SMP kernel config, but with only one CPU available).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.
Fixes: #18657
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The sleep test was checking that the sleep took no longer than "2
ticks" longer than requested. But "2 ticks" for fast tick rate
configurations can be "zero ms", and for aliasing reasons it's always
possible to delay for 1 unit more than requested (becuase you can
cross a millisecond/tick/whatever boundary in your own code on either
side of the sleep). So that "slop" value needs to be no less than
1ms.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Test needs trivial modification to account for new APIC timer code.
Eventually CONFIG_APIC_TIMER_IRQ, CONFIG_LOAPIC_TIMER_IRQ, etc. will
be consolidated into one CONFIG_TIMER_IRQ to reduce the noise a bit.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
We missed converting DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ to
DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ_0.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Using void pointers as universal arguments is widely used. However, when
compiling a 64-bit target, the compiler doesn't like when an int is
converted to a pointer and vice versa despite the presence of a cast.
This is due to a width mismatch between ints (32 bits) and pointers
(64 bits). The trick is to cast to a widening integer type such as
intptr_t and then cast to
void*.
When appropriate, the INT_TO_POINTER macro is used instead of this
double cast to make things clearer. The converse with POINTER_TO_INT
is also done which also serves as good code annotations.
While at it, remove unneeded casts to specific pointer types from void*
in the vicinity, and move to typed variable upon function entry to make
the code cleaner.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add LiteX timer driver with bindings for this device.
Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
We needed to add support for the RV32M1_LPTMR_TIMER to the test so its
knows what the IRQ of the timer is.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rewritten Xtensa CCOUNT driver along the lines of all the other new
drivers. The new API permits much smaller code.
Notably: The Xtensa counter is a 32 bit up-counter with a comparator
register. It's in some sense the archetype of this kind of timer as
it's the simplest of the bunch (everything else has quirks: NRF is
very slow and 24 bit, HPET has a runtime frequency detection, RISC-V
is 64 bit...). I should have written this one first.
Note also that this includes a blacklist of the xtensa architecture on
the tests/driver/ipm test. I'm getting spurious failures there where
a k_sem_take() call with a non-zero timeout is being made out of the
console output code in interrupt context. This seems to have nothing
to do with the timer; I suspect it's because the old timer drivers
would (incorrectly!) call z_clock_announce() in non-interrupt context
in some contexts (e.g. "expiring really soon"). Apparently this test
(or something in the IPM or Xtensa console code) was somehow relying
on that on Xtensa. But IPM is a Quark thing and there's no particular
reason to run this test there.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When TICKLESS_KERNEL is enabled, the current time in ticks is based on
a hardware counter and not interrupt delivery (which is the whole
point of tickless), so irq-locking does not prevent time from
advancing. Disable this test in that configuration.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In the POSIX architecture, with the inf_clock "SOC", time does
not pass while the CPU is running. Tests that require time to pass
while busy waiting should call k_busy_wait() or in some other way
set the CPU to idle. This test was setting the CPU to idle while
waiting for the next time slice. This is ok if the system tick
(timer) is active and awaking the CPU every system tick period.
But when configured in tickless mode that is not the case, and the
CPU was set to sleep for an indefinite amount of time.
This commit fixes it by using k_busy_wait(a few microseconds) inside
that busy wait loop instead.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
This test was written to assume that on idle the CPU would wake up on
the next tick boundary because of the timer interrupt. No such
interrupt arrives in tickless mode and it hangs forever.
A more whiteboxy test involving setting a clock timout will have to be
written for this feature if we want to keep it on tickless systems.
Alternatively we could move this test out of tests/kernel/context and
always disable tickless.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The theory behind this test seems to be that taking an IRQ lock should
prevent the advance of the kernel's tick counter. That works on
traditional timers only. In tickless mode the timer hardware/driver
is expected to be able to give us an answer for time independent of
interrupt delivery, so the test fails spuriously. The "bug" detected
is a feature of tickless!
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The system tick count is a 64 bit quantity that gets updated from
interrupt context, meaning that it's dangerously non-atomic and has to
be locked. The core kernel clock code did this right.
But the value was also exposed to the rest of the universe as a global
variable, and virtually nothing else was doing this correctly. Even
in the timer ISRs themselves, the interrupts may be themselves
preempted (most of our architectures support nested interrupts) by
code that wants to set timeouts and inspect system uptime.
Define a z_tick_{get,set}() API, eliminate the old variable, and make
sure everyone uses the right mechanism.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On some architectures tick time cannot be expressed as integer
number of microseconds, introducing error in calculations using
sys_clock_us_per_tick variable.
This commit deprecates the sys_clock_us_per_tick variable and
replaces its usage by more precise calculations based on
sys_clock_hw_cycles_per_sec and sys_clock_ticks_per_sec.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The test was using ztest incorrectly exposing everything as one single
test function. We now have multiple tests that can be tracked back to
features and requirements.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Make it possible to run in other posix boards.
By default, if the POSIX board does not define the TICK_IRQ
just run without that part of the test, printing a note.
The place where other POSIX boards should define it, is also
clear, and should be easy to keep those lines free from merge
conflicts in the future.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
On some devices, when k_cpu_idle() was called we were getting
interrupts that were not the timer interrupt. On bbc_micro
a power clock control driver interrupt was happening instead
and k_cpu_idle() was returning without the system tick advancing,
failing the test.
The clock control interrupts seem to only happen early in device
boot; moving the idle test much later lets the test pass on this
board (and likely all other NRF5 based boards).
Issue: ZEP-2257
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The hard-coded value of 10ms doesn't take the system configured
amount of ticks per second, nor does it account for an unlucky
tick advance which causes the test to fail very intermittently
in QEMU.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I6c676bc6c5e850a8725785554cd535e32067f33e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
tests/kernel/context:
added test point to cover k_cpu_atomic_idle.
Jira: ZEP-1242
Change-Id: Id09c89fd367d527ea1087e6eb2bdba29a338ceaf
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This option is added in order to support Xtensa, which needs more stack than
other architecture. This allows having a centralized way to change stack
requirements for all tests.
This extra stack size is eaqual to 0 for most architectures, except Xtensa
which requires additional 768 bytes for each stack.
Change-Id: Ie5dcae1dfd29018d36ef35dae22dc4c1a2ecdc14
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.
The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.
Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The for loop could exit with a out of bounds (variable j) value for
the delayed_threads array, we verify for the variable value before
operating on the array
This issue was reported by Coverity
Coverity-CID: 160078
Change-Id: I6aa1cc325cc363be48cd72b2a58d0a55ec3854bc
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I43a5c5112d694efdc14c5a0bcb4cafdc196d2680
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
