The application or drivers can request the LFCLK with a given
precision and accuracy.
The driver should select the clock source which has
the lowest power consumption and still satisfies the requested
accuracy and precision.
Before this commit, this was not the case.
Consider the case where the BICR has configured the system
to have LFXO with accuracy of 20 ppm.
The existing code would have ordered the clock options as following:
```
[0] = {LFLPRC, 1000 ppm},
[1] = {LFRC, 500 ppm},
[2] = {SYNTH, 30 ppm},
[3] = {LFXO_PIERCE, 20 ppm},
[4] = {LFXO_PIERCE_HP, 20 ppm}
```
**Example 1**: The user requests the clock with an accuracy of 30 ppm.
The existing code would request the power hungry "SYNTH".
**Example 2**: The user requests a clock with an accuracy of 500 ppm.
The existing code would request the LFRC which consumes more power than
the LFXO.
This commit fixes this issue by ordering the clock sources according
to power consumption.
For the examples above we user request would result in requesting the
20 ppm LFXO.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
We have to disable eSPI pad before changing PLL sequence or sequence
will fail if CS# pin is low.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Previously, I2S_MCUX_FLEXCOMM was expected to use the external
MCLK only but it's possible for I2S_MCUX_FLEXCOMM to be sourced
from other clocks like the audio_pll_clk, in which case the
driver needs to be able to get the current clock frequency
in order to properly set dividers for requested sample rate.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Current ESP32 clock system is mixed with RTC labeling/registers,
but it doesn't implement a real-time clock (RTC) driver.
To avoid confusion and allow adding a proper RTC driver later,
this commit renames the existing RTC interface to CLOCK and make
it as a subsystem without any peripheral attached to it.
This better reflects its actual purpose as a general clock controller.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Following the new feature in the flexcomm driver to be able to wake up
from low power mode, the clock control drivers have to handle the
platform specific details, so this commit adds to the already ugly mess
that is the LPC syscon driver which is used by RW currently and makes
the required devicetree changes.
Make the console/shell uart on the FRDM_RW612 take advantage of this by
default.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
CLOCK_CONTROL_NRF_HFINT_CALIBRATION depended on the renamed
nordic,nrf-hfxo -> nordic,nrf54l-hfxo. Update config to depend on
DT_HAS_NORDIC_NRF54L_HFXO_ENABLED to match new compat name.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Implement vendor specific
z_nrf_clock_bt_ctlr_hf_get_startup_time_us() which gets the startup
time of the high frequency clock used for Bluetooth.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The Clock Security System (CSS) feature signals failure of an external
oscillator by triggering an NMI. As such, when this feature is enabled,
RUNTIME_NMI must also be enabled such that the NMI handler can be modified
to point to the appropriate function.
The STM32 clock control Kconfig checks whether the CSS has been enabled in
Device Tree, and forcefully selects RUNTIME_NMI if enabled since the driver
code will require it. However, the check has been implemented improperly:
"dt_nodelabel_has_prop" was used instead of "dt_nodelabel_bool_prop", an
error similar to using DT_NODE_HAS_PROP() instead of DT_PROP() in C code.
Since the property always exists, as long as the HSE is enabled, the
RUNTIME_NMI option is always select'ed, even if not actually required.
Use the correct Kconfig function to ensure RUNTIME_NMI is select'ed only
when it is required, instead of whenever HSE is enabled regardless of CSS.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Some RTC clock code introduced is specific to SOC_SERIES_MCXN, and
causes build failures on other SOCs.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Add the definitions of the PLL2 and PLL3 outputs for the stm32H7RS mcus
and the HCLK 5 which is clock source for the XSPI instance.
and other HCLKn for other peripherals.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Select the PLL clock source for PLL2 or PLL3 as well as main PLL
This choice is useful if main PLL is off (sysclock from fixed clock)
but PLL2 or PLL3 are on for other peripherals
All PLL must have the same source else this is an error.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Create Kconfig configuration for nrfx_clock driver and use that to export
configuration to nrfx via nrfx_kconfig. So far nrfx_kconfig was using
Kconfig flags from clock_control which created a fixed connection between
nrfx_clock and clock_control and nrfx_clock could not be used without
clock_control in Zephyr.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Remove the closed loop mode implementation for the fll16m clock.
Closed loop causes a hardware bug resulting in increased current
consumption if SoC experiences high, but within spec, temperatures.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If an on-off service records an error while transitioning to the on
state, it stays in the error state and does not allow new requests
to be made until its state is reset. Add resetting of the services
associated with particular clock controllers so that requests can
be retried after failures.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Silabs siwx91x includes a memory controller for (Quad-)SPI PSRAM. It
allows the application to use the PSRAM as if it was any other RAM.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add enabled_clock, on / off and configure support for the clocks of
the stm32mp13. Describes the peripheral clock source selection.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Rename the frac-v PLL binding into fracn in order to make it
consistent with other STM32 PLL bindings.
This commit also correct the range which should be 0 - 8191.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
On STM32MP13, a dedicated MCO enable bit within the MCO clock control
register must be set in order to activate the MCO.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The flash latency needs to be configured before switching to the high
speed clock. Set the latency based on the CH32V003 and CH32V00x
reference manual.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The PWDWN_CTLx have been adjusted to support for NPCK chips. This
commit updates powe-down control initialization for NPCXN and NPCKN chips.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Calibration process can be simplified if LF clock is always on.
Kconfig was depending on RTC being used as system clock because
that indicates LF clock being always on. Same can be done for
case when GRTC is used as system clock.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
Add clock control support for RZ/A2M
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
In some case, we may need to describe a domain clock for a device
while there is no way to configure it.
Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
