This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
It bothered me that most of the log messages started with the first
letter in the message capitalized when this one did not. Fix it!
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
A small Kconfig option change to increase the descriptor pool size as
well as a dts overlay to select which gpdma to test with is needed for
the test case.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Added an overlay file for the LPC55S36 to demonstrate
the DMA Support with the scatter_gather test.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added an overlay file for the LPC55S36 to demonstrate
the DMA Support with the loop_transfer test.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added an overlay file for the LPC55S36 to demonstrate
the DMA Support with the chan_blen_transfer test.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Show an example of the LPC DMA Kconfig to reduce RAM based on the number
of DMA channels expected to be used. In this test, only one DMA channel
is needed, so we can show an example of how to reduce RAM usage of the
driver by configuring this value appropriately.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Each SoC may have different limitation regarding DMA buffer size.
This commit places the test transfer size in Kconfig so it can
be modified accordingly.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The nucleo c031c6 was filtered due to small ram size. However, the
application did fit when builed and run with west. We add a low footprint
variant of the test to also test on platforms with smaller size but where
the application fits.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
The scatter gather test now does a transfer list of 4 and the LLI pool
config needs to be updated to match the new test requirement.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
When attempting to add a new platform and run the suite with
`twister`, it seemed to be resulting in being statically
filtered-out. Likely, the correct filter is `test_dma0`,
assuming that `test_dma*` nodes should be enumerated starting
at 0.
Verified the fix by adding `dma` as `supported` to
`boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml` and by
adding the `test_dma0` node to
`chan_blen_transfer/boards/bcm958402m2_a72.overlay`.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
The test does not appear to support 64-bit DMA
* mitigate compiler warning
* support 64-bit addressing mode with `CONFIG_DMA_64BIT`
Signed-off-by: Chris Friedt <cfriedt@meta.com>
The test does not appear to support 64-bit DMA
* mitigate compiler warning
* support 64-bit addressing mode with `CONFIG_DMA_64BIT`
Signed-off-by: Chris Friedt <cfriedt@meta.com>
The test does not appear to support 64-bit DMA
* mitigate compiler warning
* support 64-bit addressing mode with `CONFIG_DMA_64BIT`
Signed-off-by: Chris Friedt <cfriedt@meta.com>
The test does not appear to support 64-bit DMA
* mitigate compiler warning
* support 64-bit addressing mode with `CONFIG_DMA_64BIT`
Signed-off-by: Chris Friedt <cfriedt@meta.com>
This patch modifies the existing loop transfer test to allow testing for
device power state changes when starting and stopping a transfer.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Configure the tests/drivers/dma/loop_transfer
and the tests/drivers/dma//chan_blen_transfer
to run on the stm32h573i_dk : use gpdma1 or gpdma2.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change this test to use the automatically generated linker section
to place the buffer in SRAM4, instead of using the manually created
region added in 088d38f. This is in preperation of removing the
manually created section.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Add unit tests for BDMA driver.
Also requires adding additional kconfig options to allocate
the memory buffers in a specific SRAM section, because
the BDMA only has access to SRAM4.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Add DMA unit tests for BDMA driver.
Also requires adding additional kconfig options to allocate
the memory buffers in a specific SRAM section, because
the BDMA only has access to SRAM4.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
The Microchip XEC family of microcontrollers includes a
simple DMA block implementing multiple channels. DMA supports
memory to memory, memory to peripheral, and peripheral to
memory transfers. Peripheral support is limited by each
chip to I2C and SPI controllers. DMA hardware does not support
scatter-gather or linked transactions.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Ensures that the documented behavior of the API is met by implementations
through testing. By calling stop on a stopped channel the expectation is no
error occurs and is checked.
Calling start after a channel has been started is difficult to test for
as there is transfer timing involved. A once shot transfer may have
completed and the channel transition to an inactive state by itself by
the time the second start call is performed. This isn't supported by at
least gpdma today and isn't documented behaviorally so should not be
tested.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
