Disable IRQ before connecting new handler when interrupt is not
shared. This aligns intc behavior to version before PR #87369.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add drivers/interrupt_controller/intc_nxp_pint/power.h abstracting
EnableDeepSleepIRQ and DisableDeepSleepIRQ invocations from
intc_nxp_pint.c. Modify intc_nxp_pint.c to use that file.
fsl_power.c and fsl_power.h can't be built on the
mimxrt685_evk/mimxrt685s/hifi4 target, so it's excluded from it in hal_nxp.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Move initialization of 'enabled' variable together with declaration.
This fixes the following compiler error:
error: 'enabled' may be used uninitialized [-Werror=maybe-uninitialized]
This is not really an error but the compiler is tricked by the
K_SPINLOCK() macro.
Fixes: https://github.com/zephyrproject-rtos/zephyr/issues/88996
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
So far, it has been assumed that only level 2 interrupts can be shared
via the `CONFIG_SHARED_INTERRUPTS` option, but this is not true. In the
case of i.MX95, for instance, level 1 interrupt 143 is shared among EDMA
channels 30 and 31.
Due to the previous assumption, the irqsteer driver currently performs
reference counting for all level 2 interrupts aggregated by each
dispatcher and, of course, for the level 1 interrupts the dispatchers are
attached to. For instance, assuming a machine with 100 level 1 interrupts
and 1 irqsteer dispatcher attached to line 50 this would mean reference
counting is performed solely for line 50 (and the level 2 interrupts MUX'd
into this line).
Going back to i.MX95, since there's no dispatcher attached to IRQ line 143
that means there's no reference counting for it. In turn, this means that
the IRQ line can be disabled accidentally on a channel release() operation
while the other channel is active.
To protect against such cases, refactor the level1 interrupt reference
counting. Now, reference counting is performed for _all_ level 1
interrupts.
Additionally, simplify the locking logic. Ideally, there would be a lock
for each dispatcher protecting the level 2 interrupts and 1 global lock
protecting the level 1 interrupts. Instead of this approach (which is a
bit more complex), simply use a global lock for all interrupts. If finer
granularity is required then it can be added later on.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add the "_raw" suffix to the macros handling the level 1 IRQ enable and
disable operation to signify that these operations perform no refcounting.
Additionally, shorten some portions of the name.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
To avoid misconfigurations a comparision has been added which compares the
amount of reported interrupts from the VIM interrupt controller with the
configured number of interrupts via Kconfig.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
On startup the VIM interrupt controller driver had a sys_read32 call with a
bitmask instead of an address. This has been fixed.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
This patch is used to provide clic(eclic) in 64 bit riscv cpu support,
since in 64 bit riscv cpu, the clic irq table entry is also 64 bit,
so we need to use ld/sd to do irq entry load and store
Signed-off-by: Huaqi Fang <578567190@qq.com>
Added support to gicv3 driver to utilize the
extended SPI MMIO registers introduced in
GICv3.1 for the extended SPI range.
Documentation for the Extended Shared
Peripheral Interrupts extension can be found
in the ARM General Interrupt Controller
Architecture Specification:
https://developer.arm.com/documentation/ihi0069/latest/
Signed-off-by: Adam Openshaw <quic_adamo@quicinc.com>
Add indirect CSR access to access CLIC register to satisfy the current
CLIC spec (Version v0.9, 2024-06-28: Draf).
Add CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS for legacy CLIC implementation
with memory-mapped CLIC register.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add support for CLIC hardware parameters based on the hardware
implementation.
1. CLIC_PARAMETER_INTCTLBITS
Specifies the number of modifiable bit in interrupt control register.
2. CLIC_PARAMETER_MNLBITS
Specifies the number of bits are assigned to interrupt level in the
interrupt control bits.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add support for CLIC SMCLICCONFIG extension, allowing user to configure
the number of available interrupt level bits at runtime.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Temporarily disabled PMP stack guard to allow access to CLIC M-mode
register, because U-mode load/store (mstatus.MPRV=0x1,MPP=0x0) is
restricted.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update interrupt allocator to use the same driver for both
Xtensa and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Hexadecimal integer literals are signed if they can fit into a signed int,
which causes undefined behavior.
This happens here because 0xFF can fit into a signed int and then gets
left-shifted by 24, undefined behavior for signed integers.
Signed-off-by: Daniel Hajjar <daniel.hajjar16@gmail.com>
Due to historical reasons, there were two implementations of
R7FA4M1AB3CFM. However, the migration has been completed,
so the old one is now being removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add interrupt controller driver support for RZ/N2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Current system INTID calcualtion only worked for SoCs whose extended
interrupts started from IRQ 0.
Otherwise, FSL_FEATURE_IRQSTEER_IRQ_START_INDEX should be added for
system INTID.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Current interrupt allocator is not taking into account
reserved areas. In case of esp32c6, Wi-Fi isn't properly
configured, causing instability or even non-functional feature.
This adds the reserved area ranges for all risc-v based SoC and
unify the slot finding based on interrupt source.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixes a multitude of Kconfigs that wrongly appear on devices
where support is literally impossible
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
For GIC multiple views feature support, all GIC Re-distributor's
GICR_TYPER.last will be set. Because configuration view-0 can
assign non-contiguous CPUs to views other than 0, in this case
the GIC Redistributors' registers won't seem contiguous.
So the GIC driver should cope with multiple sets of redistributors
like multi-chip scenarios. In this patch we add multiple GIC
redistributor regions support in GIC redistributor iteration.
For more information, refer to the Multi view subsection
in the GIC Technical Reference Manual.
For example:
https://developer.arm.com/documentation/101516/0400/Operation-of-GIC-700/Multi-view
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
IRQ 1 is reserved for WiFi in ESP-IDF, which is used as the basis
for the Espressif HAL in Zephyr.
If IRQ 1 is used by Zephyr and too many other peripherals (e.g.
multiple UARTs) are enabled, WiFi stops working.
Marking IRQ 1 as "not available" seems to fix the issue.
Fixes#82874
Signed-off-by: Martin Jäger <martin@libre.solar>
Commit e63c6cd534 introduced device API
macros to be used by driver implementations. The DEVICE_API macro
ensures the passed API instance is placed in the corresponding iterable
section to allow for runtime checks.
Add wrapper DEVICE_API macro to all its_driver_api instances.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit adds the pfic interrupt controller driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
Instead of doing an `irq_lock()`, use per-instance spinlock instead.
Refactored out an unlocked version of `local_irq_is_enabled`
from `riscv_plic_irq_is_enabled()` to achieve that.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The `arch_proc_id()` returns the hartid of a CPU, which may not start
from zero. The way that it's used as an index to access `save_irq[]`
array is wrong, use `arch_curr_cpu()->id` instead.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
In case of multiple OSes running on different CPU Cores which share the
same GIC controller, need to avoid the distributor re-configured to avoid
crash the OS has already been started.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Initialize the 'enabled' variable before using it.
This fixes the following compilation warning:
"warning: 'enabled' may be used uninitialized [-Wmaybe-uninitialized]"
issued when compiling with `CONFIG_DEBUG` enabled.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Tested-by: Daniel Baluta <daniel.baluta@nxp.com>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add support for PM. The strategy is as follows:
1) For level 1 interrupts: don't care, these don't
require the PM domain of irqsteer to be turned on
since they are, well, direct.
2) For level 2 interrupts: use the reference count
of the dispatchers.
Upon doing a get() on a dispatcher with its reference count
set to 0, before enabling the IRQ (meaning accessing the
reg. space) increment the reference count of the irqstr device
(which will result in the PM domain being enabled if 0).
Upon doin a put() on a dispatcher with its reference count
set to 1, after disabling the IRQ (meaning accessing the
reg. space) decrement the reference count of the irqstr device
(which will result in the PM domain being disabled if 0).
In summary, the PM domain of the device will be enabled if
at least one dispatcher is in use. On the other hand, the
PM domain of the device will be disabled if there's no
dispatchers in use (assuming there's no other dependencies).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, all dispatcher interrupts are enabled during
the driver init() function, which will cause a bus fault
unless the PM domain associated with irqsteer is powered on.
Since PM will be done during irq_enable()/irq_disable(),
add support for dynamically enabling/disabling dispatchers.
This way, the reg. space of the dispatchers will be accessed
when the PM domain is powered on.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, shared interrupts pose a big problem because
irq_disable() doesn't keep track of the number of clients
using that interrupt line. As such, add a reference count
mechanism which will stop the interrupt from being disabled
if there's still clients using it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Convert the compilation of the trigger type feature to depend
on Kconfig, following the same pattern of software-triggered
interrupt.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Implement `riscv_plic_irq_set_pending()` to trigger a
software-generated interrupt.
The "4. Interrupt Pending Bits" of the riscv-plic specs
described the reading of the pending bits, but not the writing
Since not all PLIC implementations support software-generated
interrupt, the function is compiled only when
`CONFIG_PLIC_SUPPORTS_SOFT_INTERRUPT` is enabled on PLIC that
supports it, such as the Andes' NCEPLIC100.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
