On the STM32H735G-DK Discovery kit, when connecting a UART from
pin PF7 to PF6, the test uart_async_api passes now.
Signed-off-by: Benjamin Deuter <benjamin.deuter@gmail.com>
Run this test on lpuart10 with internal loopback enabled.
Use DTCM region for this test because in some local
variables are used for dma buffer which requires
non-cacheable
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
change pins for the test uart_async_api loopback because the old pins
pb10/pb11 are now used for the I2C loopback test.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This includes new overlays for boards supporting DMA, and one more test
to verify M0 boards both with and without DMA can be built when
requesting CONFIG_UART_ASYNC_API.
Signed-off-by: Diego Elio Pettenò <flameeyes@meta.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
It is the arduino_i2c node on the board.
Also remove comment from arduino_r3_connector as the arduino_i2c
node can be used.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Configure the overlay to have DMA transfer with high priority
when running the tests/drivers/uart/uart_async_api on nucleo_f103rb.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds overlay and config for xmc45_relax_kit.
The Kconfig entry CONFIG_SPEED_OPTIMIZATIONS=y must be set
to pass the test at baudrate 921600 bps.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Use the macro as defined by the
include/zephyr/dt-bindings/dma/stm32_dma.h to configure the
dma channel.
Use the STM32_DMA_PERIPH_TX or STM32_DMA_PERIPH_RX value.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Align configuration for nrf52840dk to use the same loopback pins
for uart_async_api and uart_mix_fifo_poll tests.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit configures the testcase to run on the
stm32u5x5 target boards. USART2 is selected
Pins Tx and Rx (PD5 PD6 on CN9) must be connected on the HW board
to pass the test.
The USART transfer uses the GP DMA transfer with request
27 and 26 on 2 DMA channels (0-15).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit configures the testcase to run on the
stm32u585 target boards. USART3 is selected
Pins Tx and Rx (PD8 PD9 on CN14) must be connected on the HW board
to pass the test.
The USART transfer uses the GP DMA transfer with request
28 and 29 on 2 DMA channels (0-15).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure through an overlay file, the nucleo_wb55rg board
for running the tests/drivers/uart/uart_async_api.
DMAMUX is used for transfer on channels 0 & 1 with
LPUART peripheral request 17 & 16.
No hw flowcontrol for this test.
Connect pin A0 & A1 of CN8 to PASS the test.
Note that I2C3 pin assignment might conflict (PC0 & PC1).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This PR adds support for the RT1060_EVKB as a variant of the RT1060 EVK.
Blinky app tested locally on RT1060_EVKB.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
This sets the dts of dma for using the uart 6 asynch api.
The stm32f746 has a dma V1 with request 5 for Tx/Rx usart6
The Tx&Rx pins (PG14, PG9) of the usart6 are connected
on the nucleo_f746zg board to pass the test
The CONFIG_DCACHE=n must also be set to disable Dcache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This sets the dts of dma for using the uart 6 asynch api.
The stm32f767 has a dma V1 with request 5 for Tx/Rx usart6
The Tx&Rx pins (PG14, PG9) of the usart6 are connected
on the nucleo_f767zi board to pass the test
The CONFIG_DCACHE=n must also be set to disable Dcache.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
As now the CONFIG_NOCACHE_MEMORY is not responsible for controlling the
data cache on STM32H7 SoC, the CONFIG_DCACHE=n must be set explicitly
to preserve previous behavior as UART driver is not using no-cache
buffers.
Considering the above comment, the CONFIG_NOCACHE_MEMORY can be safely
removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
add nxp,loopback mode to boards with LPUART. This will enable testing
the UART async api without a physical loopback connection.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
define uart peripheral that can be connected as a loopback using
external jumper for all boards this test can be run against.
Additionally, all RT boards require DMA memory to be noncacheable. Move
SRAM to DTCM for all RT10xx series boards, and to noncacheable OCRAM for
RT11xx series.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This update Atmel sam serial drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the pinctrl state name (default) for the UART/USART/LPUART
peripherals. Changes performed using the following Python script run
from the repository root:
```
from pathlib import Path
import re
for fpath in Path(".").glob("boards/arm/**/*.dts"):
lines = open(fpath).readlines()
is_stm32 = False
for line in lines:
if "stm32" in line:
is_stm32 = True
break
if not is_stm32:
continue
with open(fpath, "w") as f:
for line in lines:
f.write(line)
m = re.match(r"(\s+)pinctrl-0.*us?art.*", line)
if m:
f.write(m.group(1) + "pinctrl-names = \"default\";\n")
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit corrects the DMA channels for the asynchronous
UART API testing support on the SAM R21 Xplained Pro board.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
It enables the usart6 to run the testcase with a DMA
tests/drivers/uart/uart_async_api. DMA2 (of type V1)
is configured on channel 5 (request) streams 7 & 2.
USART Tx and Rx PG14 - PG9 pins (14 & 16 of CN10)
are connected to PASS the test.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This sets the dts of DMA for using pn the uart 2 i.
The stm32h723 has a DMAMUX and request are 44 and 43 for usart2
The Tx&Rx pins PD5 and PD6 of the usart2 are connected
on the nucleo_h723zg board to pass the test
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add configuration for testing the usart3 through the dma1
on the nucleo_l152re target.This test requires the Tx pin
to be connected to the RX pin on the board.
Pin definition is added for this usart instance.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Based on the new bindings for the stm32 dma feature,
the overlay for enabling the dma on uart client is modified.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit configures usart3 to use dma in uart_async_api test
on nucleo_l552ze_q platform.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit configures usart3 to use dma in uart_async_api test
on stm32l562e_dk platform. Short pin2(PC10) & pin 3 (PC11) of usart3
in CN4 connector on stm32l562e_dk platform.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Adds nucleo_g071rb board to the uart_async_api test.
Therefore additionally add usart1 in board definitions.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This sets the dts of dma for using the uart asynch api.
The stm32l475 has a dmamux with request 2 for Tx/Rx usart4
The Tx&Rx pins (PA0, PA1) of the usart4 are connected
on the disco_l475_iot1 board to pass the test.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
