Commit Graph

21 Commits

Author SHA1 Message Date
Guillaume Gautier
208d962eb8 drivers: clock_control: stm32 set adc prescaler in rcc
For STM32F1 and F3, set the ADC prescaler in RCC if defined in dts.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-19 10:13:26 +00:00
Findlay Feng
b0baa92f8b drivers: clock_control: stm32: LSE fix in stm32f1x
Power supply and clock need to be enabled before operating BKP

Signed-off-by: Findlay Feng <i@fengch.me>
2023-04-24 13:34:00 +02:00
Erwan Gouriou
961e4303a7 drivers: clock_control: stm32f1: Configure USB prescaler
On STM32F1 series, configure USB(/OTGFS) prescaler based on DT.
When prescaler is set, PLL output clock is not divided.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-12-22 14:43:26 +01:00
Pierre-Emmanuel Novac
0e510cc2a6 drivers/clock_control: stm32: Configure and enable PLL2
DT node "st,stm32f105-pll2-clock" already exists but was not actually used
and PLL2 was not being configured.
PLL2 is available on STM32F105/F107 and should be turned off after turning
off PLL and turned on before turning on PLL again since PLL2 can be
used as a source for PLL. Source for PLL2 is always HSE.

Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
2022-09-09 16:28:15 -04:00
Thomas Stranger
ddf3f2d735 drivers/clock_control: stm32 common allow pll also when it is not sysclk
The SOC specific implementations of the clock_stm32_ll_common driver
included the PLL specific functions only when PLL was selected as sysclock.

This commit changes the condition from "STM32_SYSCLK_SRC_PLL"
to "defined(STM32_PLL_ENABLED)".
As a result the pll could also be used as peripheral clock source
in case it is not the sysclock.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-07-04 16:41:24 +02:00
Erwan Gouriou
09217865ce drivers/clock_control: stm32_common: Implement clock source selection
Similarly to what was done on U5 and H7 clock_control drivers, enable
device clock source selection.
This is done by:
-providing implementation for clock_control_configure().
-updating clock_control_get_rate() to support various possible clock
sources (SYSCLK, PLLCLK, LSE, LSI, HSI, HSE).
-providing enable_clock() to verify requested clock source exists and
is enabled.
-adding LSI and LSE device tree based initialization to
set_up_fixed_clock_sources().

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Gerard Marull-Paretas
fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Erwan Gouriou
c4ff7d1e19 drivers/clock_control: stm32_common: Add elementary PLL configuration step
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.

To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Erwan Gouriou
d04802283b drivers/clock_control: stm32 common: Don't disable fixed clocks
Each clock should be configured individually by device tree,
don't disable them blindly.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Erwan Gouriou
e19716e5c9 include/driver/clock_control: stm32: Remove STM32_PLL_PREDIV1
Make the code coherent with the comment:
purely remove STM32_PLL_PREDIV1.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-03 16:19:06 -04:00
Fabio Baltieri
525a235fb3 clock_control: stm32f1: fix STM32_PLL_XTPRE check
This is always defined since:

755d09e149 include/drivers/clock_control: stm32: Update for STM32F1
support

So the condition has currently no effect and causes the prescaler to
always be set to /2.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
2021-05-05 08:42:53 -04:00
Erwan Gouriou
7ce1d02ba6 drivers/clock_control: stm32f1: Add explicit case for PLL source HSI
Now that we have specific bindings for STM32F100 devices,
we need dedicated treatment for PLL source HSI case.
Otherwise, we end up using undefined symbol STM32_PLL_PREDIV1.

Please note that previous code compiled, it was assigning
a wrong value to prediv. This had no consequence because
prediv value is forced in Cube LL functions.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-05-04 13:02:26 -05:00
Erwan Gouriou
755d09e149 include/drivers/clock_control: stm32: Update for STM32F1 support
Add missing macros fro STM32F1 clock configuration

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 16:41:26 +02:00
Erwan Gouriou
99f211b668 drivers/clock_controller: stm32: Prepare for dts based configuration
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.

The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.

Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 16:41:26 +02:00
Erwan Gouriou
832a0ec049 drivers/clock_control: stm32f1: Reinstanciate CLOCK_STM32_PLL_XTPRE
This reverts commit "drivers/clock_control: Remove useless
CLOCK_STM32_PLL_XTPRE config" 9be1f7e22f3b3c42009eeba15061cad3c0988b22.

Fixes #32382

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-02-19 05:22:36 -06:00
Martin Jäger
d5aff7ba3c drivers: clock_control: stm32: use generic LL headers
Use generic LL headers instead of depending on soc.h.

Signed-off-by: Martin Jäger <martin@libre.solar>
2020-11-30 15:50:03 +01:00
Erwan Gouriou
6b72fbae7c drivers/clock_control: Remove useless CLOCK_STM32_PLL_XTPRE config
CLOCK_STM32_PLL_XTPRE Kconfig symbols was made to differentiate
code between F1 soc variants with XTRE and others.
It appears that specific XTRE code handling is already in place in
LL_PLL_ConfigSystemClock_* functions that are called afterwards.
Since this piece of code is not required anymore, let's remove
the symbol.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-07-02 08:14:45 -05:00
Peter Bigot
0b0d2e640b treewide: use full path to clock_control/stm32_clock_control.h header
The build infrastructure should not be adding the drivers subdirectory
to the include path.  Fix the legacy uses that depended on that
addition.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-26 17:52:12 +01:00
Anas Nashif
a2fd7d70ec cleanup: include/: move misc/util.h to sys/util.h
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
17ddd1714c cleanup: include/: move clock_control.h to drivers/clock_control.h
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Erwan Gouriou
37c13eec7a drivers/clock_control: stm32: Factorize series specific code
RCC device could be common to various STM32 series.
Until now, PLL handling code was set in series specific files,
even if it was driving the same device than another series.
Minimize code duplication by factorizing code between series
when possible.
With this change, some series get additional features by getting
access to code developed for other series.

Additionally, while renaming the files, remove the non informative
'x' to minimize file name length

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-10 10:53:11 -04:00