Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Current divisor is 10000000 (should be 1000000).
For example, ESP32_CLK_CPU_240M / 10000000 == 24 MHz (incorrect).
Signed-off-by: Chris Wilson <christopher.david.wilson@gmail.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add device specific clock initialization, which uses
reset reason cause information to proper define
peripherals clock state.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
core-macros.h includes other files not part of the xtensa HAL, make this
esp32 specific
Fixes#31301
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.
Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
