On ACE30 platforms adding a section to the linker script isn't
enough, it should also be added to the xtensa_soc_mmu_ranges[] array.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This patch makes cosmetic changes to ace/power.c by updating comments to
Doxygen style, fixing typos, and removing an extraneous character for
improved readability and consistency.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch enhances the power management capabilities of the Intel ADSP
by ensuring that power gating states are appropriately managed based on
core activity. It prevents the primary core from entering power gating
if secondary cores are active and re-enables power gating when all
secondary cores are off, using pm_policy_state_lock_get and
pm_policy_state_lock_put functions.
The Sound Open Firmware (SOF) project currently uses a custom power
management policy to achieve these effects. With this patch, the default
power management policy can be utilized, allowing the option to disable
the custom policy while maintaining system reliability and performance
across different core states.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
There is no need for kernel/internal/smp.h as SOF does not call
z_sched_ipi(). Actually... git log over there has no mention of
z_sched_ipi() anywhere, just arch_sched_ipi().
And include <ksched.h> for source using z_sched_ipi() since
they are using scheduling functions, and would be the correct
file to include.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Intel Audio DSP ACE needs to use arch_spin_relax() to give
the bus more time to propagate the RCW transactions among
CPUs, and to avoid sending too many requests to the bus
after failing to lock spinlocks. However, the number of
NOPs results in a very big arch_spin_relax() that spans
multiple instruction cache lines, and requires evicting
them just for NOPs. With 5 CPUs, it can span 6 cache
lines (if using nop.n instead of nop). That's a waste of
space and cache. So instead, we do a tight loop instead.
Since the SoC supports zero-overhead loops, this should
have minimal performance impact.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For some weird unknown reasons, the simulator really do not
like the cpuhold_* variables to be tightly packed together.
This results in cpuhold_spawned not being updated, and we
will be stuck in the while loop for it to be set.
Workaround this by explicitly aligning these variables on
16 byte boundary. This seems to work for now.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch will set MMU permissions for rom_ext sections
It is possible to call the rom_ext code located in IMR
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will set MMU permissions for .cold* sections
Fixes cold section execution if MMU is enabled
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
CONFIG_ADSP_POWER_DOWN_HPSRAM may not be defined (when it's "n") so
update the code accordingly so that power_down() is called with
correct parameters.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add support for .cold and .coldrodata sections, used to implement
a cold module. Assigning code and read-only data to those sections
makes them suitable for use in a cold module, stored and executed in
slow memory.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This reverts commit 3d3ffa2c05.
The original commit aimed to prevent NULL pointer accesses by moving the
MMU mapping starting point one page later. However, this change has
caused a regression on PTL. Our DSP has registers with addresses lower
than 0x1000, and the firmware uses addresses starting from 0xC40. For
instance, the HDAMLDMICL register is located at 0xCC0, which is now
inaccessible due to the change.
Reverting this commit restores access to these critical registers and
resolves the regression issue.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This puts the syscall helpers into the vector code section, and
is a tiny TLB optimization. Before this, worst case scenario is
that there would 2 instruction TLB misses when both the syscall
helpers and the vector code pages are not in TLB cache. With
this change, there would be at most 1 instruction TLB miss as
now the syscall helper and the vector code (which includes
exception handling code and xtensa_do_syscall()) are now in
the same page, and the same TLB entry.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The MMU mapping in SoC covers 0x0 which prevents catching NULL
pointer accesses. Since there are no hardware registers at
the very first page of memory, we move the starting point one
page later.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace hardcoded register addresses and values in
asm_memory_management.h with Devicetree (DT) macros for LPSRAM
power-down operations. This change ensures that register addresses and
bank counts are dynamically obtained from the Devicetree, improving code
portability and reducing the risk of errors due to manual updates.
- Removed hardcoded LSPGCTL address definitions.
- Updated m_ace_lpsram_power_down_entire macro to use DT_NODELABEL to
fetch LPSRAM bank count and control register address
- Adjusted bit field extraction logic to align with the updated register
information from the Devicetree.
This commit aligns with the ongoing effort to utilize Devicetree for
hardware abstraction and to facilitate easier maintenance and updates to
the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the m_ace_hpsram_power_change macro from asm_memory_management.h
as it is no longer used after refactoring the power_down function to
utilize the new m_ace_hpsram_power_down_entire macro. This cleanup helps
to reduce code complexity and maintainability.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Refactor the power_down function to utilize the newly introduced
m_ace_hpsram_power_down_entire macro for shutting down the entire
HPSRAM. This change simplifies the power-down process by replacing the
previous segment-based power gating mask approach with a single boolean
flag that indicates whether the entire HPSRAM should be disabled.
The function signature of power_down has been updated to accept the new
boolean flag, and the corresponding call sites have been modified to
pass the flag based on the CONFIG_ADSP_POWER_DOWN_HPSRAM Kconfig option.
Additionally, the assembly code has been cleaned up to remove the
now-obsolete hpsram_mask array and related logic.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Introduce a new assembly macro, m_ace_hpsram_power_down_entire, which
utilizes Zephyr Devicetree macros to power down the entire HPSRAM on
Intel ADSP ACE platforms.
This macro dynamically retrieves the HPSRAM bank count and control
register address from the Devicetree, streamlining the power-down
process. The macro is designed to iterate over all HPSRAM banks and
issue a power down command to each, ensuring a complete shutdown of the
HPSRAM when required by the system's power management policy.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit improves the readability of the power_down.S assembly file
by standardizing the indentation of the preprocessor definitions.
No functional changes have been made; this is purely a cosmetic update
to the code formatting.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit addresses an issue on platforms with an MMU where a
LoadStoreTLBMissCause exception occurs when accessing hardware registers
during the power-down process. The exception arises when attempting to
access the IPC register after HPSRAM has been powered down, leading to a
double exception: LoadStoreTLBMissCause followed by
InstrPIFDataErrorCause.
To resolve this, we preload the IPC register before shutting down
LPSRAM. This change prevents the double exception by ensuring that the
page table entries are correctly managed in the TLB before HPSRAM is
powered down and allowing the power-down sequence to complete
successfully.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
No functional changes were made in this update.
Only code formatting issues were corrected.
This commit is necessary to preserve Git history
continuity for future changes involving the switch from ace30_ptl to ace30.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
This reverts parts of commit c344771d8b
related to intel_adsp soc.
There is a dependency on device initialization that was missed.
Reverting until we have a proper way for migrating to hooks.
Fixes#78880
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On platforms with enforced memory access modes, .text is read-only.
Move hpsram_mask to a cached data section to fix PTL.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This patch addresses an issue in the ACE platform power management code
where the HST domain suspend operation was performed after the IMR
context save. This resulted in the power management context being
restored with outdated values upon wake-up from D3 state, leading to a
failure to resume the HST domain correctly.
By moving the `pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV)` call
before the IMR context save, we ensure that the HST domain is suspended
with the current context, and upon resume, the power management context
has the correct information to restore the HST domain state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Assembly in power_down() in power_down.S already defines data and
code to be locked in cache when powering down SRAM. Instead of adding
another such location in power.c, move the hpsram_mask[] array into
power_down.S. This fixes hard to debug failures when shutting down
the ADSP.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit introduces a new Kconfig option `CONFIG_SRAM_RETENTION_MODE`
that allows the configuration of SRAM retention mode during the
initialization phase of the firmware boot-up process. By default, the
retention mode is enabled to maintain the existing behavior. However,
this option provides the flexibility to disable the retention mode if
needed, without modifying the Zephyr codebase.
The SRAM initialization functions `hp_sram_init` and `lp_sram_init` in
`sram.c` have been updated to conditionally set the retention mode based
on the value of this Kconfig option.
Additionally, an unused macro `DELAY_COUNT` has been removed from
`sram.c` to clean up the code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
/zephyr/soc/intel/intel_adsp/ace/power.c:46:9: warning: implicit
declaration of function 'cache_data_flush_range'; did you mean
'sys_cache_data_flush_range'? [-Wimplicit-function-declaration]
46 | cache_data_flush_range((__sparse_force void *)
| ^~~~~~~~~~~~~~~~~~~~~~
| sys_cache_data_flush_range
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.
Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
XTENSA_CCOUNT_HZ is no longer common to ACE soc series
This will fix Hz value for ACE30 platform
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
A recent commit fb53d2ef8d ("ace: power: replace pseudo-assembly
movi") contained a bug: the Xtensa "movi" assembly instruction must
be written with the immediate argument already shifted left by 8, the
compiler doesn't do that automatically. This still somehow worked on
MTL but failed on LNL. Fix both occurrences.
Fixes: #75700
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When switching off memory banks we cannot use movi with arbitrary
immediate arguments, they will be converted by the compiler to memory
accesses. Only constants within the allowed range should be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The power_down() function attempts to lock the hpsram_mask on-stack
variable in data cache, which causes an exception. Moving it to .bss
by making it static fixes it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Replace the MMU initialization call with the new MMU re-initialization
API during the core context restore process in the ACE power management
code.
The previous code was directly calling `xtensa_mmu_init()` upon
restoring the core context, which is not appropriate when the MMU
context may have been preserved during low-power states. The new
`xtensa_mmu_reinit()` API is designed to re-establish the MMU context
without overwriting the existing page table, ensuring that any runtime
changes to the MMU configuration are retained.
Changes made in this patch:
- Removed the call to `xtensa_mmu_init()` from the
`_restore_core_context()` function.
- Added a call to `xtensa_mmu_reinit()` after restoring the
miscellaneous registers.
This update aligns the ACE power management code with the correct MMU
handling procedures when recovering from low-power states, as per the
recent changes in the Xtensa MMU support.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch updates the power control and status register bitfield
definitions in the ACE30 PTL ADSP power management header to match the
documented hardware specifications. The previous definitions contained
discrepancies that did not align with the actual hardware layout,
potentially leading to incorrect assumptions and usage within the
firmware.
Changes made in this patch:
- Renamed 'rsvd0' to 'rsvd4' to accurately represent the reserved bits
starting at bit position 4.
- Removed the 'rsvd6' field, which was incorrectly defined and is not
present in the hardware register layout.
- Adjusted the bit widths for 'ioxpgs' and 'mlpgs' to correctly reflect
the number of bits these fields occupy in the hardware.
- Introduced a new 'rsvd15' field in both 'ace_pwrctl2' and
'ace_pwrsts2' structures to account for the remaining reserved bits,
ensuring the structure sizes accurately represent the full register
width.
By correcting these bitfield definitions, the firmware's power
management code will now be consistent with the actual hardware design,
improving reliability and maintainability of the codebase.
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
