file should be named after the compatible and these files where using
an incorrect vendor prefix.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Clean up dt binding descriptions and introduce titles where
needed to make board documentation pages look nice. The supported
hardware table on board documentation pages sources its data
from dt bindings, and needs succinct titles.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Some instances of DMA (dma0) can use the normal sram to store their
descriptors. In this case, it makes sense to allow the linker to
allocate the memory rather than tweaking the memory layout.
So, if the attribute silabs,sram-region is not defined, use a statically
allocated buffer.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add support for 8-channel configurable DMA controller. The driver
supports the following features:
- memory to peripheral (ch0 to ch5)
- peripheral to memory (ch0 to ch5)
- memory to memory (ch6 and ch7)
Each DMA channel is multiplexed between two or more trigger sources:
- ch0 -> SPI0_TX or UART0_RX
- ch1 -> SPI0_RX or UART0_TX
- ch2 -> LRFD or UART0_TX
- ch3 -> ADC0 or UART0_RX
- ch4 -> AES_A or LRFD
- ch5 -> AES_B or ADC0
- ch6 -> Software Event Channel 0
- ch7 -> Software Event Channel 1
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add DMA driver support for Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This patch adds an initial driver for the WCH DMA
controller. All hardware features and most interface
features are implemented.
Signed-off-by: Paul Wedeck <paulwedeck@gmail.com>
Implement DMA driver for siwx917 using UDMA peripheral. For now,
Scatter/Gather DMA is not yet supported.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Improve the silabs ldma driver to support P2M and M2P transfer. It also
adds signal binding to support source request binding in the dts.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
ST engineer has moved STM32 DMA controllers bindings under ./dma/stm32/
in Linux source code reference by this commit:
https://git.kernel.org/torvalds/c/8494ae75dde4
Signed-off-by: Haiyue Wang <haiyuewa@163.com>
Multi channels share one IRQ, add channels-shared-irq-mask on RT1180
attribution to describe the channel shared status, and add code
implementation to register the handler function for each channel
in different interrupts.
Fix legacy building warning issue
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Avoid referring to Pico 2 (the name of a board). In this context,
RPI_PICO is used to refer to the (Zephyr) `SOC_FAMILY` rather than the
Pico 1 board. This clarifies common numerical values between the RP2040
and RP2350 SoC series, and enables existing DTS files to be used with
RP2350-based boards with fewer changes.
Remove the use of Zehpyr's `CONFIG_` macros from the device tree files,
and replace them with `SOC_SERIES`-specific files. Update the driver
implementation to conditionally include the correct file. Update
documentation and samples to match.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This adds initial support for NXP SDMA controller. We make use
of NXP HAL to configure the IP.
SDMA uses BD (buffer descriptors) to describe a transfer. We create
a cyclic list of descriptors and trigger them manually at start and
later when data is available.
This is tested using Sound Open Firmware app on top of Zephyr.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Convert the numerous revision compatibles to a DT property for the
revision called nxp,version (inspired from a linux DT property from
st called st,version on their DMA).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Xilinx AXI DMA Controller is commonly used in FPGA designs.
For example, it is a part of the 1G/2.5G AXI Ethernet subsystem.
This patch adds a driver for the Xilinx AXI DMA that supports
single MM2S and S2MM channels as well as the control and status
streams used by the AXI Ethernet subsystem.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The HAL configuration binding can be done dynamically based on the
IP's address space. The `hal-cfg-index` property is more tied to
software rather than hardware so remove it as an attempt to clean
up the binding.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Remove the "required: true" attribute from the STM32 DMAMUX binding.
This is required for STM32WB0 series where the DMAMUX has no interrupt line
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
`irq0-channels` defines even-numbered channels as the default value.
Since 6 was dropped from this definition, it is added.
Also, since the maximum number of channels is 12,
remove the ones that are exceeded.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit should address the #73803 issue
where the DMA node does not provide support
for the #dma-cells binding. Peripherals should
specify one or more DMA channels via the dmas
and optionally dma-names DT properties.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
1. Update EDMA driver for version 4
2. The DMAMux module is not always present. Use the
feature define to make this optional.
3. Use the EDMA_SetChannelMux API for SoC's that supports
this feature.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
To allow EDMA configuration with the help of the DT_INST_DMAS_*
and DT_DMAS_* macros, all that a consumer node needs to know
is which channel to configure and what MUX value needs to be
used. As such, this commit allows doing this by forcing the
dma-cells property to 2, each cell representing one of the
aforementioned properties.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/dma directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit introduces a driver for NXP's eDMA IP.
The main reasons for introducing a new driver are the following:
1) The HAL EDMA wrappers don't support well different
eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new
revision had to be introduced, thus requiring a new Zephyr
driver.
2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP
don't use the DMAMUX IP (instead, channel MUX-ing is performed
through an eDMA register in the case of i.MX93).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Many driver APIs are opting to provide an `emul` driver
implementation that can be used for a number of purposes.
- providing an ideal / model driver for reference
- configurable backends
- seamless integration with device tree
- support for native posix, qemu, and any other board
- fast regression testing of app and library code
Provide an initial set of bindings for `zephyr,dma-emul` devices.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
This commit introduces the SOF host DMA driver.
This driver is used by NXP platforms in the context of
SOF's host component to copy data from the host memory
to the firmware (local) memory. This is possible because
NXP platforms can access the host memory directly w/o
an actual DMA engine.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.
For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk
Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add new dt binding for edma v3 that inherits whole dt
properties from current version. One more property is
added for SoCs that don't have separate error interrupt
id, use same id with channel interrupt
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
The current implementation iterates over all channels
even if only several channels share the same irq. This
introduces one more dt property to describe an offset
between two channels share the same interrupt id.
Beside that, the error interrupt must be put as last
element of "interrupt" dt property.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
With the current implementation, the 1st cell is not DMAMUX id
as mentioned in the bindings (0 for DMAMUX0 and 1 for DMAMUX1).
Moreover, the referenced Linux bindings is obsoleted, it was
migrated to use yaml syntax
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Added a phandle named dma-parent to get base address instead of
adding DMA as child node because it is causing a build warning
(avoid_unnecessary_addr_size) if the parent instance has
"#address-cells/#size-cells" dts properties marked required
and child doesn't have reg property. DMA doesn't have reg
as it gets the base address from parent device
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
