Added NETC ENETC nodes, MDIO node, and scmi power node which will
be used to power up NETC MIX in dtsi file.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Add GPIO A-K nodes to the device tree for STM32MP2 SoC.
Note that GPIOs are disabled by default in the STM32MP2 SoC.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add the mp2 exti2 dts to the dtsi file.
Add mp2 exti hal and ll function calls with EXTI2 instance. We use the
EXTI2 instance because it contains the GPIO interrupts in the non-secure
context. (We are trying to build the blinky sample as a first milestone)
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add the initial device tree source include (dtsi) files for the
stm32mp25 series boards, covering non-secure configuration for zephyr on
the Cortex-M33 core.
These files provide the basic hardware description, including CPU
(Cortex-M33), memory, RCC clock controller and NVIC interrupt
controller.
Key features:
- Set flash and RAM addresses to DDR memory.
- Adjust RCC peripheral address for non-secure context.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Adapt MAX32690 driver to use Wrap_MXC_CAN_Init to handle differences
in the MSDK API (see analogdevicesinc/msdk#1306) between the
MAX32690 and MAX32662.
can_driver_api.timing_min required phase_seg1 >= 3 and phase_seg2 >= 2
when configuring CAN bit timing. Both microcontrollers covered by this
driver (MAX32662, MAX32690) support values down to 1 for both of these
timing parameters.
Refer to the docs for registers CAN_BUSTIM1, CANn_BUSTIM1.
Add a can0 node to the MAX32662 dtsi.
Signed-off-by: Ioan Dragomir <ioan.dragomir@analog.com>
Add devicetree to support for Renesas RZ/V2N
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5
and M4 cores are supported here.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
This commit adds support for configuring the power/performance
profile for the siwx91x device using a generic
'power-profile' property in DeviceTree.
The property is available for NWP nodes,
allowing flexible selection of power management
profiles per application or board via overlay.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
Add ELC nodes to RA SoC DTS files and provide
device-specific ELC signal enums for Devicetree bindings
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Fixes the JEDEC-ID value of the W25Q32JVWJ on-chip flash of RT1024.
It was incorrectly set to the value for the different IS25WP064 chip.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Microchip is adding more non-MEC devices to Zephyr such as
SAM and PIC32. Each device family will have its own subfolder.
We moved the existing MEC DTSI files into a new mec subfolder.
We also updated the existing MEC boards include paths.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Use nordic,nrf-nfct-v2 compatible in the main nrf54h20 devicetree
description.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Explicitly enable `rng_hci` on nRF5340 application core boards, as the
application core dos not have access to a dedicated RNG hardware
peripheral (limited to the network core).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add support to use DMA mode with cc23x0 AES module. This consists in
specifying the DMA channels and peripherals.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
In j722s_main.dtsi, the pinctrl block must have reg length 0x2b0
As per TRM, PADCONFIG registers range from 0 to 171.
Thus, length = (171-0+1)*4 = 172*4 = 0x2b0.
Reference: https://www.ti.com/lit/ds/symlink/tda4ven-q1.pdf
Table 5.1 contains data on PADCONFIG registers.
Signed-off-by: Shreyas Shankar <s-shankar@ti.com>
Add a support for TI MSPM0 Timer which has sub module for Counter,
Timer Capture and Timer Compare.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
The temperature calibration addresses of ts-cal1-addr and ts-cal2-addr
are not shared between stm32wba5 and stm32wba6 these addresses are now
separated to the dedicated device-tree
Signed-off-by: Romain Jayles <romain.jayles@st.com>
Add support to use DMA mode with cc23x0 UART module. This consists in
specifying the DMA channels and peripherals.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add support to use DMA mode with cc23x0 ADC module. This consists in
specifying the DMA channel and peripheral.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Adds skeleton dtsi for u5f9 for u5g9 to inherit from
Moves the peripheral nodes into dtsi's that actually has the peripheral
and includes them for SoC's higher in the series where applicable.
signed-off-by: Harris Tomy <harristomy@gmail.com>
The `idma` property added in 94847be1 was removed in the re-organisation
in 306dea6f. Re-add the property at a more generic location.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add devicetree to support for Renesas RZ/G2UL
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit adds serial driver support for npck3.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The newly added mcos node contains two childreen `mco1` and `mco2` that can
be used to output different clocks on the MCO pins of the stm32g0
microcontrollers.
Signed-off-by: Andreas Schuster <andreas.schuster@schuam.de>
Adds macros to be able to use the microcontroller clock output (MCO) on the
STM32G0 microcontroller.
Signed-off-by: Andreas Schuster <andreas.schuster@schuam.de>
