The USB CDC driver is unable to process any bulk IN transfers
after receiving spurious 'Clear Feature - Endpoint Halt' request
from host due to perpetual locked state caused by previously
scheduled transfer, that will never be finished, as the endpoint's state
is set to NAK. Fix by ignoring spurious request.
Signed-off-by: Piotr Ciura <piotr.ciura@hidglobal.com>
- Reset specific configuration bits in
USB1_HS_PHYC->USBPHYC_CR before setting new values.
- Set the Frequency Selection (FSEL) bits to operate
the USB PHY Control Register at 24 MHz for proper communication.
- Enable the OTGPHY1 peripheral clock using LL_AHB5_GRP1_EnableClock.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
- Removing the unused declaration of 'ret'
in the usb_dc_stm32_init function for STM32N6.
- Ensuring the 'ret' variable is used correctly
in the pinctrl_apply_state function call.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
- Unified the handling of USB OTG HS and USB OTG FS
by removing redundant preprocessor conditionals.
- Introduced a new macro `UDC_STM32_BASE_ADDRESS`
to dynamically set the USB base address.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Enable clock and power for the OTG HS peripheral
of the STM32N6x serie
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Updated USB_DC speed definition macros for STM32 series
to handle different speed configurations
based on the SoC compatibility.
Added conditional checks for full-speed definitions
using DT_HAS_COMPAT_STATUS_OKAY for st_stm32_usb.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Add defines to avoid magic values in the dtsi.
Replace usb_dc_stm32_get_maximum_speed() with device tree property.
- Use DT_INST_STRING_UPPER_TOKEN(0, maximum_speed) to set the USB speed.
- Remove PCD_SPEED_FULL initialization.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This driver is no longer maintained. So remove the
error condition to have a build error for undefined
platforms.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The drivers still use the USBREG HAL driver which enables/disables the
interrupt by itself.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Implement the HAL callback function `HAL_PCD_ISOINIncompleteCallback` in
which the endpoint write semaphore is given back, thus allowing subsequent
writes to the endpoint after an isochronous transfer has been incompleted
(not read by the host).
This approach was chosen because it is similar to what is done in the
already implemented HAL callback `HAL_PCD_DataInStageCallback` which also
gives the write semaphore back but also calls the endpoint callback
function.
The reason for not also calling the endpoint callback function is because I
do not see any appropriate cb_status (`enum usb_dc_ep_cb_status_code`) to
pass. If passing `USB_DC_EP_DATA_IN` is okay even though "In transaction
done on this EP" is not completely true, then this should also be added.
This has been tested by setting up an isochronous endpoint, writing to it,
and verify that `HAL_PCD_DataInStageCallback` is called and subsequent
writes are possible.
Signed-off-by: Algot Axelzon <algot.axelzon@satcube.com>
Some NXP socs use USBFS0 macro as base address for accessing the USB
registers, rather than USB0.
It generates compile-time errors, since USB0 is not defined.
Fix by defining USB0 if USB0 is not defined and USBFS0 is.
Signed-off-by: Alexandre Rey <alx.rey@icloud.com>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
To remove CONFIG_PINCTRL from board side for numaker boards.
The Drivers using Pinctrl should be turning Pinctrl on
instead of the responsibility of the board.
Fixes#78619
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
In GCC 14.2.0, the keyvariable in usb_dc_ep_write is detected to be used
before initialization, even though this usage should be safe.
Fix by initializing the key variable to 0, and making the 2 if
statements explicitly checking the same value.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
This Kconfig has wrongly been added to defconfig files. It is not the
right place for it. It has never been the right place for it. Drivers
that need it should select the symbol in their Kconfig entries. Drop
PINCTL from Kconfig.defconfig and add proper select at Kconfig.sam*.
Fixes#78619
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some NXP socs with Kinetis USB do not have USB voltage regulator.
It causes build error in USB samples.
Fix it by enabling and disabling the voltage regulator only if
present.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
As per USB 2.0 specification 7.1.5.1: The voltage source on the pull-up
resistor must be derived from or controlled by the power supplied on the
USB cable such that when VBUS is removed, the pull-up resistor does not
supply current on the data line to which it is attached.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The suspended flag is checked during SOF and RESUME interrupts, and it
is modified within a delayable work item. To prevent race conditions,
this update ensures that interrupts are disabled (locking IRQs) before
modifying the suspended flag. Additionally, the RESUME interrupt is
enabled only when the USB is suspended.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
A connected state was reported as a disconnected state.
This led to wrong reports of the connected state to all systems
relying on it.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Select PINCTRL subsystem by drivers which require it.
Prevent the need from enabling this symbol at board or soc level.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
In the IT82xx2 chip, the ready bit is automatically cleared by
hardware. When setting other bits, there is a chance that the ready bit
hasn't been cleared yet, leading to unexpected USB transactions. This
change ensures that the ready bit is always set to '0' when setting the
endpoint control value.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The CONFIG_USB_MCUX_CONTROLLER_TYPE choice config
is not necessary, let's just remove it. Theoretically,
if there was an SOC with the EHCI and LPCIP3511, then
it might cause a build error, but there is no SOC
which is supported on this legacy driver that has that.
Remove all settings of it in the SOC files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The DPSRAM ports can run at different clocks, this is the default
configuration, follow the advice in the datasheet and wait 3 nop
instructions before setting the AVAILABLE bit.
It can be observed that when the controller is continuously sending data
to the host, it rarely has a 0-byte transaction instead of a short
packet. The reason for this is not easy to find, it also seems to depend
on the runtime of individual components. This may fix the problem, but
there is no sure proof that this is the solution.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This commit should deal with
fixing the way USB_MCTLR_REG
is zeroed in order to disable
the USB controller along with
its tranceiver.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit should deal with updating
the way USBD was handling the DMA
engine. Based on the #73803 request
DMA should be handled via the DMA
driver API class and not directly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
When device was resumed from sleep OUT endpoints were most
likely not enabled due to condition that checked pending transfer.
Configured OUT endpoints should be enabled (ready for RX)
if they were enabled by interfaces.
Now separate bit field enabled is added and check to
see if OUT endpoint should be ready for reception after
sleep is done.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Callback with USB_DC_EP_DATA_OUT was called directly from
interrupt handler (handle_ep0_rx()) while rest of the interrupt
conditions were not checked yet.
Some interfaces started next transfer directly from this callback
resulting in case where TX endpoint was still marked as busy
and transfer was eventually abandoned.
Now message is sent from all affected endpoints after every USB
pending interrupt is handled.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Switching from write to read on EP0 is done when data is
transmitted.
Additionally receiver is enabled when NAK is created in
response to OUT token. This may happen when host sent
ZLP before everything was transmitted.
This case flushed receiver FIFO which could lead to
setup packet corruption.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add support for automatic control of PLL for USB subsystem.
This utilized virtual USB clock present in clock control.
USB driver enables PLL when device is attached or USB
sends resume signaling.
PLL can be turned off (if application does not requested it)
when device is detached (application request)
or USB host sends suspend request.
When VBUS is not present or application did not started USB yet
PD_DOMAIN_SYS is also not acquired that allows for deep
sleep. When USB is active deep sleep will never be activated.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
When EP0 was disabled EP0 was setup to ignore setup and
out packets.
In usb_dc_ep_enable() function mask was never cleared.
It resulted in USB stop functioning after application
disabled endpoint (usb_disable()) and then tried
to enable usb again.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add Kconfig option for enabling high speed USB support for the native posix
USB controller driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
According to the Zephyr documentation, the number of bytes available
for read should be returned if the input data and length parameters are
NULL and zero, respectively. This commit corrects this behavior.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Since the fifo control register and ready bit are checked in ISR
function, this commit locks IRQ when accessing these registers to
prevent racing conditions.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit addresses some issues during the extended endpoint(ep
number is larger than 4) access. There are enable and ready bits for
each endpoint on the IT82xx2 chip. The transaction completion should be
determined by the ready and enable bits of the corresponding endpoint.
Additioinally, for non-control endpoint, the FIFO control register is
selected before writing data and cleared when the IN transaction is
completed. When an IN token interrupts, the FIFO control register
should be checked if it's selected to prevent fake tokens.
Tested with: Google spikyrock project
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
