Add option in enum phy_link_speed to disable auto-negotiation.
This allows PHY drivers to support disabling auto-negotiation.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add support for setting RGMII RX and TX internal delays via DT properties:
`ti,rx-internal-delay` and `ti,tx-internal-delay`.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
make sure that autonegotiation is restarted, after
changing the speeds. Also make sure to only write
the changed registers, as mdio is pretty slow.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
As the code noted, the RGMII RX and TX clock delay values may need to
change depending on the MAC configuration or the PCB layout. Add
properties to allow configuring these in the device tree, defaulting to
the previous hard-coded values if not present.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
rename LINK_*_*BASE_T to LINK_*_*BASE
speed options for ethernet drivers shouldn't end with a _T, implying
that ethernet is only supported via a twisted pair cable.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Looping while waiting for auto-negotiation to complete can block the
system workqueue for several seconds.
Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
Return -ENOTSUP in phy_mii_cfg_link when a fixed-link configuration is set,
indicating that MDIO read/write operations are not supported.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
* Sort includes by groups each alphabetically:
- standard lib
- zephyr
- private
* Move log registration to be after all includes.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
There were some driver bindings issues for the davicom dm8806 driver:
- Missing type for reg-switch binding
- Missing required: true for int/reset gpios
- Fix macro for reg-switch
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Energy efficient mode is the feature of the DM8806 described in the
EEE 802.3az Energy Efficient for reducing power consumption. For unknown
reason it seams to not working correctly with all endpoints and sometimes
the network randomly fails when this mode is on. Thus it is now possible to
turn off it in compile time by KConfig option:
PHY_DM8806_ENERGY_EFFICIENT_MODE if in case of network problems
Signed-off-by: Robert Slawinski <robert.slawinski.ext@indurad.com>
SMI bus error check mechanism is preventing the host SMI bus to be
interferred by noise on board level. Current implementation is checking
if data which is writing to/reading from the PHY has correct CRC sum.
If not, then writing/rading process is repeated by the number of
attempts defined in the KConfig. If repeating transmission will fail
by the numbers of ettemps defined in KConfing, drivers returns an
error.
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
Add support for LAN8670/1/2 Rev.C2 as per the latest configuration note
AN1699 released (Revision E (DS60001699F - June 2024)) for Rev.C1 is also
applicable for Rev.C2. Refer hardware revisions list in the latest AN1699
Revision E (DS60001699F - June 2024).
https://www.microchip.com/en-us/application-notes/an1699
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support for LAN8650/1 Rev.B1. As per the latest configuration note
AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also
applicable for Rev.B1. Refer hardware revisions list in the latest AN1760
Revision F (DS60001760G - June 2024).
https://www.microchip.com/en-us/application-notes/an1760
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
10BASE-T1S PHYs can operate in either CSMA/CD or PLCA mode. PLCA mode
needs some set of parameters like node id, node count, max burst count,
burst timer and TO (Transmit Oppertunity) timer to be configured. OPEN
Alliance TC14 specification defined a set of PLCA registers to configure
PLCA mode. The below APIs are implemented for PLCA mode.
genphy_set_plca_cfg() - to configure PLCA settings.
genphy_get_plca_cfg() - to get the configured PLCA settings.
genphy_get_plca_sts() - to get the PLCA status like active or inactive.
These APIs are implemented as generic library so that all 10BASE-T1S
PHYs can use these APIs to configure/access PLCA settings to avoid
duplication of code.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Simplifies GPIO reset logic in `phy_mc_ksz8081_reset()` by introducing
a dedicated function, `phy_ksz8081_reset_gpio`. If this function returns
`-ENODEV`, it will fall back to using a command-based reset instead.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Simplifies error handling in `phy_mc_ksz8081_get_link()` by
centralizing mutex unlocking with a `done` label.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Compilation will fail if both adin2111 and adin1100 are used
at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
On the interrupt handling, one thread per driver instance is involved
into monitoring the semaphor, sends inside the gpio callback triggered
by the gpio interrupt. Each time, when the link parameters are change,
the DM8806 is generating the gpio interrupt. After getting semaphor,
the application callback function which was linked during initialization
process is called to get the new link parameters with standard API
calls
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
The ICS1894 phy AN_COMPLETE bit is latched high, this make the
BMSR first read return incorrect status of the AN state, update
one more BMSR read to ensure all latched bit is clear and BMSR
return actual status of the phy chip
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
I for the life of me do not know what is going on here with the RNB chip
but it seems this override must be set in order for the chip to work,
regardless of strap-in configuration, and if not set explicitly, the
value after a reset for these two bits will be seemingly random and
inconsistent. And it was working before by luck before removing a second
redundant reset in a recent commit, because apparently the register
was getting the opposite of the reset value according to the datasheet
which makes it work. The result of these bits after reset seem to vary
depending on host mcu, board, debugger, number of times reset, type of
reset, and with a pinch of random chance after keeping all variables
seemingly the same, so let's just set it to the value that works
explicitly, even if it doesn't make sense. The bit here doesn't have
clear documentation but it seems it's for using RMII regardless of the
strap in option, which is what we want to do anyways if we know the
interface type from DT, so I think it's fine, considering it is making
this driver work again.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
500 ms reset time is only for software reset and comes from IEEE spec.
Datasheet mentions for hardware reset the assertion of the signal should
only need to be 500 us, and 100 us after deassert to wait to access
programming interface.
Also remove an unused macro.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
No need to reset in cfg link, this was blocking system workqueue during
phy callbacks that call cfg link, since this happens from monitor work
handler which is in the system workqueue.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
