For some weird reasons, if the sections in linker script are not
in memory address order, there are lots of padding involved in
zephyr_pre0.elf. This moves the .intList section to its memory
ordered location. When building hello_world, this shrinks
zephyr_pre0.elf from 512MB to 339KB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Zephyr maps start/end of rodata section with variables
using __rodata_region namespace. The exception was Xtensa.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.
As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.
Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
