Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The cortex-m7 is an implementation of armv7-m. Adjust the Kconfig
support for cortex-m7 to reflect this and drop the unnecessary,
explicit, conditional compilation.
Change-Id: I6ec20e69c8c83c5a80b1f714506f7f9e295b15d5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Precursor patches have arranged that conditional compilation hanging
on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the
config variable to reflect this.
Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Precursor patches have arranged all conditional compilation hanging on
CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support
for ARM ARMv6-M, rename the config variable to reflect this.
Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The ARM code base provides for three mutually exclusive ARM
architecture related conditional compilation choices. M0_M0PLUS,
M3_M4 and M7. Throughout the code base we have conditional
compilation gated around these three choices. Adjust the form of this
conditional compilation to adopt a uniform structure. The uniform
structure always selects code based on the definition of an
appropriate config option rather the the absence of a definition.
Removing the extensive use of #else ensures that when support for
other ARM architecture versions is added we get hard compilation
failures rather than attempting to compile inappropriate code for the
added architecture with unexpected runtime consequences.
Adopting this uniform structure makes it straight forward to replace
the adhoc CPU_CORTEX_M3_M4 and CPU_CORTEX_M0_M0PLUS configuration
variables with ones that directly represent the actual underlying ARM
architectures we provide support for. This change also paves the way
for folding adhoc conditional compilation related to CPU_CORTEX_M7
directly in support for ARMv7-M.
This change is mechanical in nature involving two transforms:
1)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
is transformed to:
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
...
2)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
#else
...
#endif
is transformed to:
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
...
#else
#error Unknown ARM architecture
#endif
Change-Id: I7229029b174da3a8b3c6fb2eec63d776f1d11e24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The cortex-m related memory map definitions in memory-map.h are all
CPU specific. In preparation for replacing
CONFIG_CPU_CORTEX_M0_M0PLUS with CONFIG_ARMV6_M and
CONFIG_CPU_CORTEX_M4_M4 with CONFIG_ARMV7_M, adjust memory_map.h
conditional compilation to hang on CONFIG_* variables for specific
cortex CPUs.
Change-Id: I2af0b75eaa5b16f88836dbdae41446beacaeba71
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set have a reduced set of registers and fields compared to
the ARMv7-M compliant processors.
This change goes through all core registers and disables or removes
everything that is not part of the ARMv6-M architecture when compiling
for Cortex-M0.
Jira: ZEP-1497
Change-id: I13e2637bb730e69d02f2a5ee687038dc69ad28a8
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set can only access the NVIC_IPRn registers with word
accesses, and not with byte ones like the Cortex-M3 and onwards. This
patch addresses the issue by modifying the way that _NvicIrqPrioSet()
writes to the IPRn register, using a word access for Cortex-M0(+).
A similar issue is addressed for internal exceptions, this time for the
SHPR registers that are accessed differently on ARMv6-M.
Reference code taken from CMSIS.
Jira: ZEP-1497
Change-id: I08e1bf60b3b70579b42f4ab926ee835c18bb65bb
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since the value is treated as uint8_t internally anyway, just use
uint8_t for the input and output parameter types.
Jira: ZEP-1497
Change-Id: I61d68eb39cba5d82dad6ab7593b267c26e003d2b
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
That module is not used anymore: it was introduced pre-Zephyr to add
some kind of awareness when debugging ARM Cortex-M3 code with GDB but
was never really used by anyone. It has bitrotted, and with the recent
move of the tTCS and tNANO data structures to common _kernel and
k_thread, it does not even compile anymore.
Jira: ZEP-1284, ZEP-951
Change-Id: Ic9afed00f4229324fe5d2aa97dc6f1c935953244
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.
The kernel internals now make use of these APIs instead of the legacy
ones.
Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but
was not registering any exception on priority 0. Only reserve priority 0
and use it for SVC and fault exceptions instead of priority 1.
Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
There are now three flags that decide how many priorities are reserved
by the kernel, each one requiring one priority level: Zero Latency
Interrupts, BASEPRI locking (for SVC usage) and faults that are not at
priority -1, so that taking them in an ISR actually triggers the fault
synchronously.
Change-Id: I7f4d760c9110051aeb82dcfd8cd68026a9b74b54
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This allows using it in _EXC_PRIO() instead of hardcoding 2 and 3.
Change-Id: I3549be54602643e06823ba63beb6a6992f39f776
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Drop the unnecessary trailing whitespace formatting in inline asm.
Change-Id: I351df91b7175fe21d268d325865838b4840def8d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Replace the use of a hardwired temporary register in the irq_lock()
implementation with a local variable. This will allow the compiler
more flexibility in register allocation.
Change-Id: Ifbdb52fca1d40404d55934343ac2a8153df7e1a8
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The cortex-m4 irq_lock() implementation uses a movs instruction, thus
clobbering the condition code, but does not include the clobber in the
asm clobber list. This is a bug in the situation where the compiler
schedules a live condition code over the inline lock instructions.
Since the irq_lock() implementation does not need to kill the CC we
simply switch to mov from movs.
Take the opportunity to drop the unnecessay .n and let the assembler
choose an appropriate encoding.
This fixes a bug found by inspection, it has not actually been
observed in real code.
Change-Id: Id60fa3362df9d4bf05c3d5e23066410ede92d73c
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Add the missing memory clobber to irq_unlock() in order to prevent the
compiler reordering memory operations over the unlock.
Change-Id: If1d664079796618ed247ff5b33b8b3f85fb7e680
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The inline asm definition of irq_lock() on the ARM architecture marks
the ASM as volatile which prevents the compiler from removing the
isntruction but does provide any information to the compiler to
prevent the inline ASM instruction being re-ordered relative to other
instructions. The instruction used in irq_lock() do not touch memory,
however in order to acheive their intended purpose they must be
ordered relative to other memory access instruction. This is acheived
by adding the "memory" clobber.
Instances of the compiler inappropriately re-ordering irq_lock() calls
relative to other instructions without this patch can be observed in
the code generated for k_sleep() on NRF51 target boards.
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Change-Id: I9d42d54cd9a50e8150c10ce6715af7ca2f5cfe51
If a particular project needs to add additional data to the
binary image, in most cases the entire linker script needs to
forked into the project space, causing maintenance issues if
the main linker script is changed.
Now we add some Kconfig options to allow a project to specify
some additional linker scripts which get included by the main
one in a few key areas:
1) In the definition to the 'rodata' section, which can allow
additional data to be included in this ROM section.
2) In the definition to the 'datas' section, which allows
additional data to be included in this RAM section.
3) Arbitrary additional sections to be included at the end of
the binary.
For 1 and 2, this is useful to include data generated outside of
the normal C compilation, such as data structures that are created
by special build tools.
3 is useful for including arbitrary binary blobs inside the final
image, such as for peripheral or co-processor firmware.
Change-Id: I5738d3d6da25f5bc96cda8ae806bf1a3fb34bd5d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Zephyr kernel is unable to compile when CONFIG_RUNTIME_NMI is enabled in
defconfig on ARM's architectures.
This patch addresses the following issues:
* In nmi.c _DefaultHandler() is referencing a function
(_ScbSystemReset()) not defined in Zephyr. This has now been replaced
with sys_arch_reboot.
* nmi.h is included in ASM files and due to the usage of "extern" the
compilation ends with an error. Added the directive _ASMLANGUAGE to
prevent the problem.
Jira: ZEP-1319
Change-Id: I7623ca97523cde04e4c6db40dc332d93ca801928
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.
x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.
Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All M7 features common to M3/M4 are working. New features like Tightly
Coupled Memory (TCM) are not yet supported.
Change-Id: I5f7b292e70843aec415728f24c973bb003014f4b
Jira: ZEP-977
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Support Cortex-M0, M3/M4, M7 is easier when the memory map is defined in
terms of absolute addresses.
Based work from: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Change-Id: I860860c369e8bed6c6c23661a15ce464d87ff221
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Not disabling SysTick as it is optional by the spec.
SVC not used as there is no priority-based interrupt masking (only
PendSV is used).
Largely based on a previous work done by Euan Mutch <euan@abelon.com>.
Jira: ZEP-783
Change-Id: I38e29bfcf0624c1aea5f9fd7a74230faa1b59e8b
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
This is used by a test case, and it's better to just put this
here instead of forking the linker scripts.
Change-Id: Ifbb90b73bb26118ae2422cc6feccb3db58a26f2c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For XIP images, in order to avoid the situation when
__data_rom_start is 32-bit aligned, but the actual data is placed
after rodata section, which may not end exactly at 32-bit border,
pad rodata section, so __data_rom_start points at data and it is
32-bit aligned.
On non-XIP images this may enlarge image size up to 3 bytes.
This is generally not an issue, since modern ROM and FLASH
memory is usually 4k aligned.
Change-Id: I3d37fccbc610615585d776144ab9e281368258d6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Binutils ld has an annoying misfeature (apparently a regression from a
few years ago) that alignment directives (and alignment specifiers on
symbols) apply only to the runtime addresses and not, apparently, to
the load address region specified with the "AT>" syntax. The net
result is that by default the LMA output ends up too small for the
addresses generated in RAM. See here for some details:
https://sourceware.org/ml/binutils/2013-06/msg00246.htmlhttps://sourceware.org/ml/binutils/2014-01/msg00350.html
The required workaround/fix is that AFAICT any section which can have
inherit a separate VMA vs. LMA from a previous section must specify an
"ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of
sync and the XIP data will be wrong at runtime.
No, I don't know why this isn't the default behavior.
A further complexity is that this feature only works as advertised
when the section is declared with the "AT> region" syntax after the
block and not "AT(address)" in the header. If you use the header
syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply
padding and the LMA ends up to big. This is almost certainly a
binutils bug, but it's trivial to work around (and the working syntax
is actually cleaner) so we adjust the usage here.
Note finally that this patch includes an effective reversion of commit
d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which
was an earlier workaround for what seems to be the same issue.
Jira: ZEP-955
Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Merge the Cortex-M3/M4 memory map bits into the master memory map in
prep for it being shared with Cortex-M7 support and Cortex-M0 support
going forward.
Change-Id: I211fc2a2d7d49082b51463f06e6e71cca75d886f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to the memory pool structure only static declaration of
memory pool is possible.
Change-Id: I4797ed88fd2ac3b7812ff26e552e1745611c4575
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Add _arch_irq_is_enabled external interrupt API to find out
if an IRQ is enabled.
Change-id: I8ccbaa6d4640c1ab8369d2d35c01a2cfbb02f6cd
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
In 1.0 you could set only one callback on the whole gpio controller. It
was impossible for another sub-system to add another callback, without
overwritting an existing one.
Such API has been obsolete for a long time and no one is using it
anymore. Thus removing it entirely.
Change-Id: I6a17fd99373dc6cef1fa2ebb421e992412d5015e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Commit 3e63a74514 did not revert properly
things.
Change-Id: I792d5698966542ce2cfb9f858c56b30c392f02a2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Follow up to TSC decission for further discussion in the networking
WIG.
Change-Id: I148b484dfe308661573e47ed3e60cceed673bddf
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Net core then does not know anything about l2 related logic.
For instance ARP is used in ethernet l2 API and nowhere else.
This will be helpful when adding different technologies altogether.
Currently, only SLIP driver is enabled to use relevant l2 layer.
Change-Id: I03c93326321028d04222733ca4083e3c6b785202
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will be used by the new network stack to relate a device to actual
network context, and used in the different layers (mac, ip ...).
Change-Id: I30c08fa975314544c36b71636fd9653d562891b3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Updates the exception stack frame structure to include floating point
registers.
Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Many sub-systems might require to set a callback on different pins.
Thus enabling it via changing the API.
It is also possible to retrieve private-data in the callback handler
using CONTAINER_OF() macro (include/misc/util.h).
Former API is still available, and is emulated through the new one.
Using both should not be a problem as it's using new API calls.
However, it's now better to start using the new API.
Change-Id: Id16594202905976cc524775d1cd3592b54a84514
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The nmi_on_reset.S functions are used by all ARM platforms. It
makes no sense to repeat the same code for all platforms. Moving
the code from each SOC implementation to arch/arm/core.
The same treatment for the NMI_INIT() macro. Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.
Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
