For testing/debugging purposes, it will be possible then to register
or unregister an i2c target.
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
When using target mode, we've found that some times the msg field can
be null through some of the code paths of the interrupt event handler.
Signed-off-by: Yuval Peress <peress@google.com>
Some macros haven't been properly renamed in previous commits.
Fixes the wrong names that caused compilation errors.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Only include cmsis_core.h on ARM platforms, including it unconditionally
as it is now causes a build failure on all other platforms, namely x86
on the weekly build run.
Tested with:
west build -p -b up_squared/apollo_lake tests/drivers/build_all/led
(and others)
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Follow-up to PR #88631: fix missing variable declarations introduced in
the STM32 I2C LL driver after adding timeouts to blocking loops.
The missing declarations caused a build failure when interrupts were
disabled (CONFIG_I2C_STM32_INTERRUPT=n).
Fixes a regression introduced in #88631.
Signed-off-by: Jean Nanchen <jean.nanchen@gmail.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
'timings' is an array of 'struct i2c_config_timing' (3 x uint32_t).
'i2c_timings_##index' is an array of uint32_t (hence the cast when it
is assigned to 'timings'). Therefore 'ARRAY_SIZE(i2c_timings_##index)' is
off by a factor 3 when used for n_timings.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Fix npcx_i2c_ctrl_transfer arguments to match header to prevent
warning: type of 'npcx_i2c_ctrl_transfer' does not match original
declaration
Signed-off-by: Al Semjonovs <asemjonovs@google.com>
Remove redundant ifdef exclusion of calls to
pm_policy_device_power_lock_get() and
pm_policy_device_power_lock_put().
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Since the __IO macro use has been removed, make the whole reg pointer
volatile. This is similar to what is done in the gpio-davinci driver.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Some I2C peripherals like TI charger or gauge chips need support for I2C
clock stretching. This patch includes that and makes these modules
usable with I2C emulation over GPIO.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
base on DesignWare I2C driver to implement RTS5912 I2C driver.
1. support customize bus recovery function.
2. fix isr timing issue by enable tx empty control.
3. support stuck at low handle by enable bus clear feature.
4. support custom stuck at low timeout set from dts
5. disable block mode in rts5912 i2c.
6. support I2C_ALLOW_NO_STOP_TRANSACTIONS
Signed-off-by: Titan Chen <titan.chen@realtek.com>
The current I2C driver assumes that at least one byte will be read in CQ
(command queue) mode. However, when a 0-byte read is issued
(e.g., by cmd_i2c_scan),
The read handler uses (len - 1) to set the command queue length.
When len is 0, this underflows to 0xFF, leading to an incorrect transfer
length and possible crash.
To fix this, add a check in cq_mode_allowed() for reads with length 0:
-Fallback to PIO mode in such cases.
-Properly handle 0-byte reads by issuing STOP (E_FINISH) when the slave
address is acknowledged.
-Add appropriate handling for NACK conditions when the slave address is
not acknowledged.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
`timings` is an array of `struct i2c_config_timing` (3 x `uint32_t`).
`i2c_timings_##index` is an array of `uint32_t` (hence the cast when it
is assigned to `timings`). Therefore `ARRAY_SIZE(i2c_timings_##index)` is
off by a factor 3 when used for `n_timings`.
Parentheses around the second `sizeof` are there to silence the gcc warning
(-Wsizeof-array-div) that warns about not computing the size of
`i2c_timings_##index`.
Signed-off-by: Wouter Horré <wouter@versasense.com>
Fix issue where STM32 I2C LL driver could block forever when SDA and SCL
are shorted and interrupts are disabled (CONFIG_I2C_STM32_INTERRUPT=n).
Added timeouts to all blocking wait loops in the STM32 LL I2C driver to
avoid indefinite blocking.
Fixes#88506
Signed-off-by: Jean Nanchen <jean.nanchen@hevs.ch>
- Use DEVICE_MMIO_* macros for getting the registers.
- These macros automatically used the proper RAM/ROM address.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add the device name to the error logs so we can differentiate which
device caused the error and not just which port.
Signed-off-by: Yuval Peress <peress@google.com>
Adds the simplest possible I2Cv1 controller driver for STM32 with the RTIO
interface. Currently only interrupt driven transfers are supported.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Adds the simplest possible I2Cv2 controller driver for STM32 with the RTIO
interface. Currently only interrupt driven transfers are supported.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Co-authored-by: Tom Burdick <thomas.burdick@intel.com>
In preparation of the introduction of the STM32 I2Cv2 RTIO driver, move
some functions that are used in both drivers into a common file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Rename all functions and macros starting by stm32_i2c_* to i2c_stm32_* to
harmonize the driver.
Reformat some indents for better alignment.
Remove i2c_stm32_get_config function declaration from header since it is
not used.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Changed to define ambiq spi/i2c dma mode as a binding property
instead of kconfig macros, making it more flexible for different
spi/i2c instances.
Signed-off-by: Hao Luo <hluo@ambiq.com>
1. rework IOM cmdq buffer instantiation
2. rework spi and i2c cache handling as it is incorrect.
3. buffers need to be aligned with DCACHE on
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add stub functions for the I2C DMA callbacks, which are invoked
during or upon completion of DMA-based I2C transactions. Without
these, NULL pointer calls occur on DMA transfer complete or error
events, leading to faults within ISR context.
Signed-off-by: Simon Gilbert <srdgilbert@gmail.com>
Call i2c_rtio_complete with a non-zero status code in case of an error
so that application does not get stuck waiting for the completion queue
event. An example to this situation could be an I2C target device
responding with a NACK to a read or write request by the controller.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The I2C shell allows a user to input "i2c scan i2c0" for instance, to
scan addresses on the i2c0 bus enabled in DT. This currently causes
an infinite loop when CONFIG_I2C_MAX32_INTERRUPT is enabled.
The infinite loops happens because 0-length transactions
(tx_len == rx_len == 0) not being handled both by the Async
i2c_max32_transfer and by the controller ISR.
This commit makes two changes:
1) [ISR] When an address ACK is received, if there is simply no data to
send or receive, then just give up the semaphore, preventing the
i2c_max32_transfer function from waiting infinitely.
2) [i2c_max32_transfer] After getting the semaphore back, if there is no
data to send or receive, then avoid waiting for the BUSY flag to clear
since clock stretching should not occur by definition for transactions
which merely contain an address ACK.
Signed-off-by: Brandon Hurst <brandon.hurst@analog.com>
Replace the manually implemented GPIO-based I2C recovery logic
with Zephyr's i2c_bitbang API.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Determine if lpflexcomm wrapped lpi2c by instance and connect
irq differently dependending on that to support platforms with
both flexcomm wrapped and unwrapped lpi2c's.
Applying c1286a8d8d425805fcceb3b872325fb4c439a572 to RTIO version.
Authored-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Luis Ubieda <luisf@croxel.com>
The Low Power Flexcomm driver manages the interrupt handling
and provides an API to register interrupt callbacks.
Register the NXP LPI2C interrupt handler.
Applying dca6e64c93f26db254089f20225854bb1f8fe9b4 on RTIO-version.
Authored-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Some NXP SoC's have a FlexComm interface that manages the
interrupts.
Applying 482e39ea9556f53adbb7f67d0d0da3d17bbbae90 on RTIO-version.
Authored-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Luis Ubieda <luisf@croxel.com>
